Motorola Corporation

Symbol Technologies, LLC

Other

Google Inc.

Freescale Semiconductor,inc.

Papu D Maniar

Reza Moazzami

Robert W Fiordalice

Robert E Jones

C Joseph Mogab

Yi Wei

Jeffrey L Klein

Jon T Fitch

Keith E Witek

Hao Li

Bernard J Roman

Stephen S Poon

Faivel S Pintchovski

Sergio A Ajuria

Arkalgud R Sitaram

Andrew C Campbell

Jerry Gelatos

Wei E Wu

Shawn George Thomas

Howard C Kirsch

Chris C Yu

Kenneth Andrew Dean

Peter Zurcher

Vida Ilderem

Kevin G Kemp

John J D'Urso

Jeffrey T Wetzel

John R Yeargain

Robert Edwin Jones, Jr

Keshu Zhang

Haifeng Li

Roc Blumenthal

Peir Chu

Li Hao

A device () with a viewable surface () including a plurality of transparent pedestals () having a reflective material () disposed on its sides () make smudges forming thereon unnoticeable by taking advantage of optical characteristics including contrast and the user's visual acuity. The pedestals () generally have a width () of less than 50 microns, a height () equal to twice the width (), and a spacing () between adjacent pedestals () equal to the width (). The device () may be an electronic device, and more particularly a portable electronic device such as a cell phone.

Viewable surface having unnoticeable smudges

A transparent force sensor for use in touch panel displays (touch screens) and method for fabricating the same are disclosed. The transparent force sensor is capable of detecting touch by measuring local pressure applied by a touch input to a display area of the touch screen.

Transparent force sensor and method of fabrication

Methods and apparatus are provided for manipulating content displayed on a touch screen utilizing a transparent pressure-sensing touch panel. A method comprises displaying content on the touch screen and obtaining one or more pressure metrics for an input gesture on the transparent pressure-sensing touch panel. Each pressure metric corresponds to pressure (or force) applied to the transparent pressure-sensing touch panel by a respective impression of the input gesture. The method further comprises adjusting the displayed content on the touch screen in response to the input gesture, wherein the displayed content is adjusted based on to the one or more pressure metrics for the input gesture.

Methods and apparatus for pressure-based manipulation of content on a touch screen

Methods and apparatus are provided for depositing a layer of pure germanium can on a silicon substrate. This germanium layer is very thin, on the order of about 14 &#x212b;, and is less than the critical thickness for pure germanium on silicon. The germanium layer serves as an intermediate layer between the silicon substrate and the high k gate layer, which is deposited on the germanium layer. The germanium layer helps to avoid the development of an oxide interfacial layer during the application of the high k material. Application of the germanium intermediate layer in a semiconductor structure results in a high k gate functionality without the drawbacks of series capacitance due to oxide impurities. The germanium layer further improves mobility.

Interfacial layer for use with high k dielectric materials

Method for forming a semiconductor device having an capacitor, where the capacitor is in-laid in a cavity formed in the semiconductor substrate and part of a high density memory. One embodiment first forms a bottom electrode in the cavity and then fills the cavity with a sacrificial layer to allow chemical mechanical polishing (CMP) of at least one of the capacitor electrodes. After removing portions of the bottom electrode and portions of the sacrificial layer, a dielectric layer is formed. A top electrode is then formed over the dielectric layer. The dielectric layer so formed isolates the bottom electrode from the top electrode preventing shorting and leakage currents. In one embodiment, a single top electrode layer is formed for multiple bottom electrodes, reducing the complexity of the memory circuit.

Method for forming a semiconductor device

An improved contact structure and process for forming an improved contact structure for a semiconductor device. A metal (14) is formed on a first metal layer (12) positioned on a substrate (10) The metal (14) is a Group VIIB or Group VIII metal or metal oxide and increases the electrically conductive surface area (25) of the first metal layer (12). In one embodiment, a Group VIIB or Group VIII metal layer is deposited onto the first metal layer and the Group VIIB or Group VIII metal layer is anisotropically etched to form sidewall spacers (24). An insulating layer (16) is deposited overlying the first conductive layer (12) and the sidewall spacers (24). A via opening (18) is formed in the insulation layer (16) to expose a portion of the electrically conductive surface area (25). A second metal layer (22) fills the opening (18) and forms a metallurgical contact to the first metal layer (12).

Method of making a contact structure

A semiconductor device (11) has a spin on glass layer or region, and the spin on glass has a method of synthesis and use. The spin on glass composition is formed which comprises on the order of 0% to 20% by volume of tetraethylorthosilicate (TEOS), on the order of 0.01% to 20% by volume of tetraethylorthogermanate (TEOG), on the order of 0% to 1% by volume the equivalent of nitric acid (HNO.sub.3), on the order of 70% to 85% by volume of alcohol, and a remaining balance of the spin on glass composition being water. The spin on glass is applied to a semiconductor substrate and heated and/or densified to form the spin on glass layer or region.

Germanium silicate spin on glass semiconductor device and methods of

In on form, a TEOS based spin-on-glass is made having on the order of 10% to 25% by volume of tetraethylorthosilicate, the equivalent of on the order of 0.1% to 3.0% by volume of 70% concentrated nitric acid, on the order of 60% to 90% by volume of alcohol, and the balance water. The spin-on-glass is applied to a semiconductor substrate and heated in order to densify the spin-on-glass.

Process for making a semiconductor device having a TEOS based

A method for forming vias in a semiconductor device improves the resistance and reliability of contacts formed by use of an etch stop layer during the via formation process. An etch stop layer (40), preferably a silicon nitride or aluminum nitride layer, is deposited over conductive interconnect (34). A via (44) is etched in interlayer dielectric (42), stopping on etch stop layer (40). Etch stop layer (40) is then anisotropicly etched to expose the top of conductive interconnect (34), while maintaining a portion of the etch stop layer along a sidewall of the interconnect, and particularly along those sidewall portions which contain aluminum. A conductive plug (54) is then formed in the via, preferably using one or more barrier or glue layers (50). Formation of a tungsten plug using tungsten hexafluoride can then be performed without unwanted reactions between the tungsten source gas and the aluminum interconnect.

Method for forming a via in a semiconductor device

A capacitor with a metal-oxide dielectric layer is formed with an upper electrode layer that is electrically connected to an underlying circuit element. The capacitor may be used in forming storage capacitors for DRAM and NVRAM cells. After forming an underlying circuit element, such as a source/drain region of a transistor, a metal-oxide capacitor is formed over the circuit element. An opening is formed through the capacitor and extends to the circuit element. An insulating spacer is formed, and a conductive member is formed that electrically connects the circuit element to the upper electrode layer of the metal-oxide capacitor. Devices including DRAM and NVRAM cells and methods of forming them are disclosed.

Capacitor having a metal-oxide dielectric

A trench isolation region (32) is fabricated to include a trench liner (28) comprised of aluminum nitride. The aluminum nitride trench liner is useful in borderless contact applications wherein a contact opening (56) is etched in an interlayer dielectric (54) and overlies both an active region. (e.g. doped region 52) and the trench isolation region. During formation of opening using etch chemistry which is selective to aluminum nitride, the trench liner protects a P-N junction at a corner region (58) of the trench to prevent exposing the junction. By protecting the junction, subsequent formation of a conductive plug (60) will not electrically short circuit the junction, and will keep diode leakage to within acceptable levels.

Method for providing trench isolation

A trench isolation region (32) is fabricated to include a trench liner (28) comprised of aluminum nitride. The aluminum nitride trench liner is useful in borderless contact applications wherein a contact opening (56) is etched in an interlayer dielectric (54) and overlies both an active region (e.g. doped region 52) and the trench isolation region. During formation of opening using etch chemistry which is selective to aluminum nitride, the trench liner protects a P-N junction at a corner region (58) of the trench to prevent exposing the junction. By protecting the junction, subsequent formation of a conductive plug (60) will not electrically short circuit the junction, and will keep diode leakage to within acceptable levels.

Method for providing trench isolation and borderless contact

Self-aligned silicide regions (24) are formed in a semiconductor device (10) using vapor phase reaction. A chemical vapor deposition system (40) is used, but rather than depositing a blanket silicide material, a precursor (48) is introduced into the reaction chamber (42) and reacts with only exposed silicon and polysilicon members of the device. The reaction is assisted by heating the substrate to a temperature at which the precursor is volatile. Because the precursor source reacts only with exposed silicon and polysilicon regions, subsequent etch steps are unnecessary. In one form, cobalt silicide regions are formed using a cobalt carbonyl as the precursor source.

Method for forming self-aligned silicide in a semiconductor device using

Process for forming a capacitor having a metal-oxide dielectric

In the present invention, an inlaid interconnect (44) is formed by chemical mechanical polishing. A polish assisting layer (31), in the form of an aluminum nitride layer, is formed between an interlayer dielectric (30) and an interconnect metal (42) to prevent dishing or cusping of the interconnect upon polishing. By allowing the sacrificial polish assisting layer (31) to be removed at close to the same rate as interconnect metal (42) during the final stages of polishing, dishing is avoided. The aluminum nitride layer also facilitates chemical vapor deposition of aluminum as the interconnect metal by providing a more suitable nucleation site for aluminum than exists with silicon dioxide.

Growing community of inventors

Austin, TX, United States of America

Papu D Maniar