Intel Corporation

Intel Mobile Communications Gmbh

Paolo Madoglio

Stefano Pellerano

Georgios Yorgos Palaskas

Ashoke Ravi

Ofir Degani

Zdravko Boos

Hasnain Lakdawala

Bernd-Ulrich Klepser

Rotem Banin

Peter Preyler

Kailash Chandrashekar

Seunghee Han

Andreas Menkhoff

Stephan Henzler

Markus Schimper

Dirk Friedrich

Michael Bruennert

Marian K Verhelst

Hyung Seok Kim

Peter Pawliuk

Andreas Boehme

Yee W Li

Pin-En Su

Byungho Park

An apparatus can include baseband processing circuitry to generate at least one artificial channel function for combining with at least one multiple-input multiple-output (MIMO) layer input to a precoder. The baseband processing circuitry can also provide the combined artificial channel function and MIMO layer input to the precoder. The apparatus can also include circuitry to transmit a channel based on the combined artificial channel function and MIMO layer input. Other systems and methods are also described.

PAPR reduction for correlated CDM groups

Modulation circuitry is configured to generate a phase modulated signal having an output frequency that corresponds to a local oscillator (LO) signal divided by N.5. A phase locked loop (PLL) is configured to generate an LO signal having a frequency that is N.5 times the output frequency. Pulse circuitry configured to generate, based at least on a value of N, an edge signal including a pulse aligned with a positive edge of the LO signal and a pulse aligned with a negative edge of the LO signal. The edge signal is used to generate the phase modulated signal.

Modulation circuitry with N.5 division

This application discusses, among other things, apparatus and methods for sharing a local oscillator between multiple wireless devices. In certain examples, an apparatus can include a central frequency synthesizer configured to provide a central oscillator signal having a first frequency, a first transmitter, the first transmitter including a first transmit digital-to-time converter (DTC) configured to receive the central oscillator signal and to provide a first transmitter signal having a second frequency, and a first receiver, the first receiver including a first receive DTC configured to receive the central oscillator signal and to provide a first receiver signal having a first receive frequency.

Direct digital frequency generation using time and amplitude

A digital to time converter (DTC). The DTC includes a lookup table, a divider, a thermometric array and a switched capacitor array. The lookup table is configured to generate one or more corrections based on thermometric bits of an input signal. The divider is configured to generate a plurality of divider signals from an oscillator signal based on the one or more corrections. The thermometric array is configured to generate a medium approximation signal from the plurality of divider signals based on the one or more corrections. The switched capacitor array is configured to generate a digital delay signal from the medium approximation signal based on the one or more corrections and switched capacitor bits of the input signal.

Digital time converter systems and methods

This document discusses apparatus and methods for reducing energy consumption of digital-to-time converter (DTC) based transmitters. In an example, a wireless device can include a digital-to-time converter (DTC) configured to receive phase information from a baseband processor and to provide a first modulation signal for generating a wireless signal, and a detector configured to detect an operating condition of the wireless device and to adjust a parameter of the DTC in response to a change in the operating condition.

Power saving technique for digital to time converters

Digital time converter systems and method

Representative implementations of devices and techniques provide a phase multiplexer that may be associated with at least a communication device. The described phase multiplexer may be able to switch between input phases without distorting a pulse width of a given input phase. In one implementation, this is achieved by enabling one phase at a time. More specifically, a gating window specific for each given phase is provided. The gating window is designed to avoid glitches associated with signals at an output of the phase multiplexer. Furthermore, the gating window is designed to avoid the generation of pulse width modifications.

Phase multiplexer

This application discusses, among other things, calibration systems for ameliorating nonlinearity of a digital-to-time converter (DTC). In an example, a calibration system can include a calibration path configured to represent a segment of the DTC, a time-to-digital circuit configured to receive an output of the calibration path and the processed frequency information and to provide timing error information of the segment, and a calibration engine configured to receive controller modulation information from a main controller, to provide calibration modulation information to the DTC, to receive the timing error information, and to provide compensation information to a correction circuit coupled to the DTC using the timing error information.

Segmented digital-to-time converter calibration

Representative implementations of devices and techniques provide a time delay based on an input value. A digital delay may be generated based on a coarse delay and a fine delay. The coarse delay may be selected based on the input value. The fine delay may be selected from an overlapping set of fine delay intervals, based on the selected coarse delay. In some implementations, a control component may be used to select the fine delay when more than one fine delay interval is indicated.

Redundant delay digital-to-time converter

This document discusses, among other things, digital-to-time converters (DTCs) and more particularly to parallel implementations of DTCs. In an example, an apparatus can include a first digital-to-time converter (DTC) configured to receive reference frequency information and first phase information of a polar transmitter and to provide a first portion of phase modulation information, a second DTC configured to receive second phase information of the polar transmitter and to provide a second portion of phase modulation information, and a combiner configured to receive the first portion and the second portion and to provide a phase modulated signal.

Parallel digital-to-time converter architecture

Embodiments of the present disclosure provide methods, systems, and apparatuses related to an open-loop digital delay-locked loop having a drift sensor. Other embodiments may be described and claimed.

Digital delay-locked loop with drift sensor

Disclosed is a method and apparatus to extend TDC resolution to better than 1 ps without incurring a matching and power penalty. Higher resolution can be achieved by segmenting the resolution between a mismatch free re-circulating time-to-digital converter (RTDC) and a stochastic time-to-digital converter (STDC). The disclosed RTDC replicates the same delay element to eliminate mismatch with the required dynamic range (200 ps for a 5 GHz example) and moderate resolution (3-5 ps typical corresponding to 6-7 bits for the 5 GHz case). While the STDC can achieve a resolution of 50 fs but with a range of only 3-5 ps which also corresponds to approximately 6-7 additional bits by exploiting process variations and mismatch to achieve a very fine resolution with limited dynamic range.

Sub-picosecond resolution segmented re-circulating stochastic time-to-digital converter

A device article and method for an open loop calibrated phase wrapping phase modulator. A tapped delay line may provide a coarse resolution for one or more phases of a signal. A phase multiplexer may receive one or more coarse phases from the tapped delay line and select a coarse phase to send to the digitally controlled delay line. A digitally controlled delay line may provide a fine resolution to the coarse phase from the phase multiplexer.

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Beaverton, OR, United States of America

Paolo Madoglio