Intel Corporation

Netlogic Microsystems, Inc

Raza Microelectronics, Inc.

Alcatel Lucent

Sycamore Networks, Inc.

Broadcom Corporation

Rmi Corporation

Paolo L Narvaez

Eliezer Weissmann

Alon Naveh

Dheeraj R Subbareddy

Eugene Gorbatov

David A Koufaty

Ganapati Srinivasa

Scott D Hahn

Mishali Naik

Andrew J Herdrich

Inder M Sodhi

Russell Jerome Fenger

Gaurav Khanna

Paul Brett

Abirami Prabhakaran

Andrew D Henroid

Murat Bog

Michael Mishaeli

Bret L Toll

Jason W Brandt

Ravishankar Iyer

Stephen Anthony Fischer

Ashish V Choubal

Peretz Moshe Feder

Aamer Jaleel

Hisham Shafi

Rinat Rappoport

Nagabhushan Chitlur

Naimish Patel

Oron Lenz

Kenzo Van Craeynest

Gary S Tse

Sanjeev S Sahagirdar

Efraim Rotem

Ronny Ronen

Boris Ginzburg

Joel S Emer

Bryant E Bigbee

Anil Aggarwal

Yuval Yosef

Tong Li

Richard A Barry

Hisham Abu-Salah

Murat Azizoglu

Ilya Osadchiy

Kayi Lee

Anthony Chi-Kong Kam

Farzana I Khatri

Guarav Khanna

Avi Mendleson

Lama Mouayad

Russel J Fenger

A heterogeneous processor architecture and a method of booting a heterogeneous processor is described. A processor according to one embodiment comprises: a set of large physical processor cores; a set of small physical processor cores having relatively lower performance processing capabilities and relatively lower power usage relative to the large physical processor cores; and a package unit, to enable a bootstrap processor. The bootstrap processor initializes the homogeneous physical processor cores, while the heterogeneous processor presents the appearance of a homogeneous processor to a system firmware interface.

Method for booting a heterogeneous system and presenting a symmetric core view

A processor of an aspect includes at least one lower processing capability and lower power consumption physical compute element and at least one higher processing capability and higher power consumption physical compute element. Migration performance benefit evaluation logic is to evaluate a performance benefit of a migration of a workload from the at least one lower processing capability compute element to the at least one higher processing capability compute element, and to determine whether or not to allow the migration based on the evaluated performance benefit. Available energy and thermal budget evaluation logic is to evaluate available energy and thermal budgets and to determine to allow the migration if the migration fits within the available energy and thermal budgets. Workload migration logic is to perform the migration when allowed by both the migration performance benefit evaluation logic and the available energy and thermal budget evaluation logic.

Selective migration of workloads between heterogeneous compute elements based on evaluation of migration performance benefit and available energy and thermal budgets

In one embodiment, the present invention includes a multicore processor with first and second groups of cores. The second group can be of a different instruction set architecture (ISA) than the first group or of the same ISA set but having different power and performance support level, and is transparent to an operating system (OS). The processor further includes a migration unit that handles migration requests for a number of different scenarios and causes a context switch to dynamically migrate a process from the second core to a first core of the first group. This dynamic hardware-based context switch can be transparent to the OS. Other embodiments are described and claimed.

Providing an asymmetric multicore processor system transparently to an operating system

A heterogeneous processor architecture is described. For example, a processor according to one embodiment of the invention comprises: a set of large physical processor cores; a set of small physical processor cores having relatively lower performance processing capabilities and relatively lower power usage relative to the large physical processor cores; virtual-to-physical (V-P) mapping logic to expose the set of large physical processor cores to software through a corresponding set of virtual cores and to hide the set of small physical processor core from the software.

Apparatus and method for heterogeneous processors mapping to virtual cores

A system and method are provided for performing Local Center Authorization Service (LCAS) in a network system, the system having a data aligner configured to align bytes of input data according to groups of members. The system also including an LCAS control manager configured to generate desequencing control commands in response to data input from the data aligner. The system further including a de-sequencer configured to de-sequence the input data input from the data aligner according to desequencing control commands received from the LCAS control manager.

System and method for performing concatenation of diversely routed channels

A heterogeneous processor architecture is described. For example, a processor according to one embodiment of the invention comprises: a set of two or more small physical processor cores; at least one large physical processor core having relatively higher performance processing capabilities and relatively higher power usage relative to the small physical processor cores; virtual-to-physical (V-P) mapping logic to expose the set of two or more small physical processor cores to software through a corresponding set of virtual cores and to hide the at least one large physical processor core from the software.

Hetergeneous processor apparatus and method

A heterogeneous processor architecture is described. For example, a processor according to one embodiment of the invention comprises: a first set of one or more physical processor cores having first processing characteristics; a second set of one or more physical processor cores having second processing characteristics different from the first processing characteristics; virtual-to-physical (V-P) mapping logic to expose a plurality of virtual processors to software, the plurality of virtual processors to appear to the software as a plurality of homogeneous processor cores, the software to allocate threads to the virtual processors as if the virtual processors were homogeneous processor cores; wherein the V-P mapping logic is to map each virtual processor to a physical processor within the first set of physical processor cores or the second set of physical processor cores such that a thread allocated to a first virtual processor by software is executed by a physical processor mapped to the first virtual processor from the first set or the second set of physical processors.

A processor is described having an out-of-order core to execute a first thread and a non-out-of-order core to execute a second thread. The processor also includes statistics collection circuitry to support calculation of the following: the first thread's performance on the out-of-order core; an estimate of the first thread's performance on the non-out-of-order core; the second thread's performance on the non-out-of-order core; an estimate of the second thread's performance on the out-of-order core.

Processor scheduling with thread performance estimation on cores of different types

In a method for over-the-air provisioning of a mobile terminal in a wireless network, a first transaction between the mobile terminal and a web server is performed via an external port. During the first transaction, the mobile terminal obtains user subscription information for subscribing to network services. During a second transaction between the web server and the mobile terminal, the mobile terminal obtains device management information for authorizing the mobile terminal to access the network services. The first and second transactions are conducted via the same external port.

Web-based over-the-air provisioning and activation of mobile terminals

A system and method are provided for performing Local Centre Authorization Service (LCAS) in a network system, the system having a data aligner configured to align bytes of input data according to groups of members. The system also including an LCAS control manager configured to generate de-sequencing control commands in response to data input from the data aligner. The system further including a de-sequencer configured to de-sequence the input data input from the data aligner according to de-sequencing control commands received from the LCAS control manager.

Methods and devices for initial bootstrap of a user terminal are provided. The user terminal transmits at least one first message to an initial bootstrap server. The first message includes device management capability information for the user terminal. The initial bootstrap server selects a device management protocol to be used by the user terminal and sends the selected device management protocol to the user terminal in at least one second message.

Methods for initial bootstrap during activation and initial configuration of user terminals in network

A system and method for policing of access to resources in a heterogeneous data redirection device is disclosed. The invention utilizes Random Early Detection to determine whether or not a given packet should be dropped or accepted into the resource. The invention uses a combination of different metrics each of which utilizes a different version of RED. Schemes can include a Per-Flow Weighted RED metric, a Global RED metric and a Fair Share Pool metric, where shared resource allocation is dependent dynamically upon the number of users at the time a packet requests access. These metrics can be combined in variety of ways to yield a final drop or accept decision for an incoming packet so that it does not access resources.

Mechanism for managing access to resources in a heterogeneous data redirection device

A system and method are provided for performing Local Center Authorization Service (LCAS) in a network system, the system having a data aligner configured to align bytes of input data according to groups of members. The system also including an LCAS control manager configured to generate de-sequencing control commands in response to data input from the data aligner. The system further including a de-sequencer configured to de-sequence the input data input from the data aligner according to de-sequencing control commands received from the LCAS control manager.

System and method for performing concatentation of diversely routed channels

A system and method for classification of data units in a network device acts as a bridge in heterogeneous networks, provides many different services and provisions many different transport mechanisms. The data classifier generates an ID that is internally used by the network device in managing, queuing, processing, scheduling and routing to egress the data unit. This internal ID enables the device to accept any type of data units from any physical/logical ports or channels and output those data units on any physical/logical ports or channels that are available. The device utilizes learning on a per-flow basis and can enable the device to identify and process data units used in private line services and private LAN services.

Method and device for the classification and redirection of data packets in a heterogeneous network

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Mountain View, CA, United States of America

Paolo L Narvaez