Intel Corporation

Paolo Gargini

Mark A Holler

George J Korsh

George Perlegos

Israel Beinglass

Norman Ahlquist

An improved floating gate MOS EPROM cell which is programmable at a lower potential (12 volts) than prior art devices which often require 25 volts. The oxide thickness between the floating gate and overlying control gate is thicker at the edges of the floating gate than in the central portion. The thicker oxide at the edges prevents uncontrolled DC erasing. This allows a thinner oxide to be used in the central portion and provides the increased capacitance coupling needed for programming at a lower potential.

Method of making EPROM cell with reduced programming voltage

A process is described for forming MOS circuits which include underlying polysilicon members such as gate members covered with metal. In one embodiment, a self-aligning tungsten process is used to cover the polysilicon members. Low temperature 'rear end' steps are used to prevent deterioration of the underlying metal. For example, a plasma nitride protective layer is used to cover the metal. The polysilicon/metal members provide reduced resistance and increase the speed of the resultant MOS circuits.

Method of making MOS device by forming self-aligned polysilicon and

EPROM Cell with reduced programming voltage and method of fabrication

Growing community of inventors

Palo Alto, CA, United States of America

Paolo Gargini