Hewlett Packard Enterprise Development LP

Hewlett-packard Development Company, L.p.

Hewlett-packard Company

Stmicroelectronics Gmbh

Other

Paolo Faraboschi

Dejan S Milojicic

Naveen Muralimanohar

John Paul Strachan

Mark Owen Homewood

Robert S Schreiber

Chris I Dalton

Martin Foltin

Catherine Graves

Gary Lee Vondran, Jr

Sheng Li

Sai Rahul Chalamalasetti

Norman Paul Jouppi

Gregg Bernard Lesartre

Gary Belgrave Gostin

Mark David Lillibridge

Giuseppe Desoli

Moray McLaren

Dwight L Barron

Anthony Jarvis

Rajeev Balasubramonian

Parthasarathy Ranganathan

Derek Alan Sherlock

Michael R Krause

Andrew Christopher Walton

Kimberly Keeton

Doe Hyun Yoon

Steven J Simske

Cullen Edwin Bash

Jan Morovic

Peter Morovic

Nigel John Edwards

Mehul A Shah

Jichuan Chang

Jeffrey Clifford Mogul

Vanish Talwar

Suparna Bhattacharya

Alan Lynn Davis

Qiong Cai

Daniel Ortega

Geoffrey M Brown

Sergey Serebryakov

Cong Xu

Kirk M Bresniker

Ayose J Falcon

Alexander J Starr

Joseph A Fisher

Sherif Yacoub

Prasad A Raje

Jishen Zhao

Jose Abad Peiro

Alexandros Daglis

Ping Chi

Anirban Nag

Abhishek Gupta

Ayose Falcon Samper

Geoffrey Ndu

Kevin T Lim

Yuan Chen

Charles Stuart Johnson

Daniel Juergen Gmach

Harvey Ray

Antonio Lain

Jose Renato G Santos

Shawn Kenneth Walker

Roland John Burns

Andrew Mackenzie

Emiliano Bartolome

Vasanth Bala

Lluis Abello

Manuel Gonzalez

Paul G Emerson

Gerd Zellweger

Andreu Gonzalez

Aalap Tripathy

Al Davis

Richard L Ford

Izzat El Hajj

Alexander Merritt

Juan Manuel Garcia Reyero Viñas

Annmary Justine Koomthanam

Sudarsun Kannan

Virginia Palacios

Itir Akgun

Stanko Novakovic

Adit Madan

Alberto Such-Vicente

Kaisheng Ma

Gabriel Parmer

Eduardo Argollo De Oliveira Dias, Jr

Anthony X Jarvis

Systems and methods are provide for automatically constructing data lineage representations for distributed data processing pipelines. These data lineage representations (which are constructed and stored in a central repository shared by the multiple data processing sites) can be used to among other things, clone the distributed data processing pipeline for quality assurance or debugging purposes. Examples of the presently disclosed technology are able to construct data lineage representations for distributed data processing pipelines by (1) generating a hash content value for universally identifying each data artifact of the distributed data processing pipeline across the multiple processing stages/processing sites of the distributed data processing pipeline; and (2) creating an data processing pipeline abstraction hierarchy for associating each data artifact to input and output events for given executions of given data processing stages (performed by the multiple data processing sites).

Method to track and clone data artifacts associated with distributed data processing pipelines

A crossbar array includes a number of memory elements. An analog-to-digital converter (ADC) is electronically coupled to the vector output register. A digital-to-analog converter (DAC) is electronically coupled to the vector input register. A processor is electronically coupled to the ADC and to the DAC. The processor may be configured to determine whether division of input vector data by output vector data from the crossbar array is within a threshold value, and if not within the threshold value, determine changed data values as between the output vector data and the input vector data, and write the changed data values to the memory elements of the crossbar array.

Acceleration of model/weight programming in memristor crossbar arrays

Systems and methods are provided for incorporating an optimized dispatcher with an FaaS infrastructure to permit and restrict access to resources. For example, the dispatcher may assign requests to 'warm' resources and initiate a fault process if the resource is overloaded or a cache-miss is identified (e.g., by restarting or rebooting the resource). The warm instances or accelerators associated with the allocation size that are identified may be commensurate to the demand and help dynamically route requests to faster accelerators.

Optimal dispatching of function-as-a-service in heterogeneous accelerator environments

A method of computing in memory, the method including inputting a packet including data into a computing memory unit having a control unit, loading the data into at least one computing in memory micro-unit, processing the data in the computing in memory micro-unit, and outputting the processed data. Also, a computing in memory system including a computing in memory unit having a control unit, wherein the computing in memory unit is configured to receive a packet having data and a computing in memory micro-unit disposed in the computing in memory unit, the computing in memory micro-unit having at least one of a memory matrix and a logic elements matrix.

Methods and systems for computing in memory

A technique includes, in response to a cache miss occurring with a given processing node of a plurality of processing nodes, using a directory-based coherence system for the plurality of processing nodes to regulate snooping of an address that is associated with the cache miss. Using the directory-based coherence system to regulate whether the address is included in a snooping domain is based at least in part on a number of cache misses associated with the address.

Using a directory-based cache coherence system to regulate snooping

Disclosed techniques provide for dynamically changing precision of a multi-stage compute process. For example, changing neural network (NN) parameters on a per-layer basis depending on properties of incoming data streams and per-layer performance of an NN among other considerations. NNs include multiple layers that may each be calculated with a different degree of accuracy and therefore, compute resource overhead (e.g., memory, processor resources, etc.). NNs are usually trained with 32-bit or 16-bit floating-point numbers. Once trained, an NN may be deployed in production. One approach to reduce compute overhead is to reduce parameter precision of NNs to 16 or 8 for deployment. The conversion to an acceptable lower precision is usually determined manually before deployment and precision levels are fixed while deployed. Disclosed techniques and implementations address automatic rather than manual determination or precision levels for different stages and dynamically adjusting precision for each stage at run-time.

Adjustable precision for multi-stage compute processes

A computer system includes multiple memory array components that include respective analog memory arrays which are sequenced to implement a multi-layer process. An error array data structure is obtained for at least a first memory array component, and from which a determination is made as to whether individual nodes (or cells) of the error array data structure are significant. A determination can be made as to any remedial operations that can be performed to mitigate errors of significance.

Determining significance levels of error values in processes that include multiple layers

Techniques for a firewall to determine access to a portion of memory are provided. In one aspect, an access request to access a portion of memory within a pool of shared memory may be received at a firewall. The firewall may determine whether the access request to access the portion of memory is allowed. The access request may be allowed to proceed based on the determination. The operation of the firewall may not utilize address translation.

Firewall to determine access to a portion of memory

According to examples, a system may include a central processing unit (CPU) and a capability enforcement controller in communication with the CPU. The capability enforcement controller may be separate from the CPU and may implement capability processing functions that control capabilities. Capabilities may be defined as unforgeable tokens of authority that protect access by the CPU to a physical address at which the data is stored in a memory.

Capability enforcement controller

Computer-implemented methods, systems, and devices to perform lossless compression of floating point format time-series data are disclosed. A first data value may be obtained in floating point format representative of an initial time-series parameter. For example, an output checkpoint of a computer simulation of a real-world event such as weather prediction or nuclear reaction simulation. A first predicted value may be determined representing the parameter at a first checkpoint time. A second data value may be obtained from the simulation. A prediction error may be calculated. Another predicted value may be generated for a next point in time and may be adjusted by the previously determined prediction error (e.g., to increase accuracy of the subsequent prediction). When a third data value is obtained, the adjusted prediction value may be used to generate a difference (e.g., XOR) for storing in a compressed data store to represent the third data value.

Floating point data set compression

In one example, a central processing unit (CPU) with dynamic thread mapping includes a set of multiple cores each with a set of multiple threads. A set of registers for each of the multiple threads monitors for in-flight memory requests the number of loads from and stores to at least a first memory interface and a second memory interface by each respective thread. The second memory interface has a greater latency than the first memory interface. The CPU further has logic to map and migrate each thread to respective CPU cores where the number of cores accessing only one of the at least first and second memory interfaces is maximized.

Dynamic thread mapping

Example implementations relate to a capability enforcement processor. In an example, a capability enforcement processor may be interposed between a memory that stores data accessible via capabilities and a system processor that executes processes. The capability enforcement processor intercepts a memory request from the system processor and enforces the memory request based on capability enforcement processor capabilities maintained in per-process capability spaces of the capability enforcement processor.

Capability enforcement processors

In some examples, with respect to adaptive multi-level checkpointing, a transfer parameter associated with transfer of checkpoint data from a node-local storage to a parallel file system may be ascertained for the checkpoint data stored in the node-local storage. The transfer parameter may be compared to a specified transfer parameter threshold. A determination may be made, based on the comparison of the transfer parameter to the specified transfer parameter threshold, as to whether to transfer the checkpoint data from the node-local storage to the parallel file system.

Adaptive multi-level checkpointing

Growing community of inventors

Palo Alto, CA, United States of America

Paolo Faraboschi