Micron Technology Incorporated

Intel Corporation

Paolo Fantini

Lorenzo Fratin

Massimo Ferro

Fabio Pellizzer

Enrico Varesi

Alessio Spessot

Agostino Pirovano

Corrado Villa

Swapnil Lengade

Andrea Redaelli

Mario Allegra

Innocenzo Tortorelli

F Daniel Gealy

Thomas M Graettinger

Alessandro Calderoni

Cristina Casellato

Daniele Ielmini

Nicola Ciocchini

Marco Bernasconi

Silvia Gabardi

Ferdinando Bedeschi

Marco Sforzin

Paolo Amato

Paolo Tessariol

Andrea Martinelli

Claudio Nava

Stephen W Russell

Efrem Bolandrina

Stefan Frederik Schippers

Kuo-Wei Chang

Patrick M Flynn

Innocenzo Totorelli

Swapnil A Lengade

A memory cell may include a first electrode, a second electrode, and a self-selecting storage element between the first electrode and the second electrode. The self-selecting storage element may extend between the first electrode and the second electrode in a direction that is parallel with a plane defined by the substrate. The self-selecting storage element may also include a bulk region and a sidewall region. The bulk region may include a chalcogenide material having a first composition, and the sidewall region may include the chalcogenide material having a second composition that is different than the first composition. Also, the sidewall region may extend between the first electrode and the second electrode.

Sidewall structures for memory cells in vertical structures

Methods, systems, and devices for a decoding architecture for memory devices are described. Word line plates of a memory array may each include a sheet of conductive material that includes a first portion extending in a first direction within a plane along with multiple fingers extending in a second direction within the plane. Memory cells coupled with a word line plate, or a subset thereof, may represent a logical page for accessing memory cells. Each word line plate may be coupled with a corresponding word line driver via a respective electrode. A memory cell may be accessed via a first voltage applied to a word line plate coupled with the memory cell and a second voltage applied to a pillar electrode coupled with the memory cell. Parallel or simultaneous access operations may be performed for two or more memory cells within a same page of memory cells.

Decoding architecture for word line tiles

The present disclosure provides a memory device and accessing/de-selecting methods thereof. The memory device comprises a memory layer including a vertical three-dimensional (3D) memory array of memory cells formed therein, wherein a memory cell is accessed through a word line and a digit line orthogonal to each other, and the digit line is in a form of conductive pillar extending vertically; a pillar selection layer formed under the memory layer and having thin film transistors (TFTs) formed therein for accessing memory cells; and a peripheral circuit layer formed under the pillar selection layer and having a sense amplifier and a decoding circuitry for word lines and bit lines, wherein a TFT is configured for each pillar.

Vertical 3D memory device and accessing method

Methods, systems, and devices for a decoding architecture for memory devices are described. Word line plates of a memory array may each include a sheet of conductive material that includes a first portion extending in a first direction within a plane along with multiple fingers extending in a second direction within the plane. Two word line plates in a same plane may be activated via a shared electrode. Memory cells coupled with the two word line plates sharing the electrode, or a subset thereof, may represent a logical page for accessing memory cells. A memory cell may be accessed via a first voltage applied to a word line plate coupled with the memory cell and a second voltage applied to a pillar electrode coupled with the memory cell. Parallel or simultaneous access operations may be performed for two or more memory cells within a same page of memory cells.

Decoding architecture for memory devices

Methods, systems, and devices for a memory device with laterally formed memory cells are described. A material stack that includes a conductive layer between multiple dielectric layers may be formed, where the conductive layer and dielectric layers may form a channel in a sidewall of the material stack. The channel may be filled with one or more materials, where a first side of an outermost material of the one or more materials may be exposed. An opening may be formed in the material stack that exposes a second side of at least one material of the one or more materials. The opening may be used to replace a portion of the at least one material with a chalcogenide material where the electrode materials may be formed before replacing the portion of the at least one material with the chalcogenide material.

Memory device with laterally formed memory cells

A memory cell may include a first electrode, a second electrode, and a self-selecting storage element between the first electrode and the second electrode. A conductive path between the first electrode and the second electrode may extend in a direction away from a plane defined by a substrate. The self-selecting storage element may include a bulk region and a sidewall region. The bulk region may include a chalcogenide material having a first composition, and the sidewall region may include the chalcogenide material having a second composition that is different than the first composition. The bulk region and sidewall region may extend between the first electrode and the second electrode and in the direction away from the plane defined by the substrate.

Memory cells with sidewall and bulk regions in planar structures

A vertical 3D memory device may comprise: a substrate including a plurality of conductive contacts each coupled with a respective one of a plurality of digit lines; a plurality of word line plates separated from one another with respective dielectric layers on the substrate, the plurality of word line plates including at least a first set of word lines separated from at least a second set of word lines with a dielectric material extending in a serpentine shape and at least a third set of word lines separated from at least a fourth set of word lines with a dielectric material extending in a serpentine shape; at least one separation layer separating the first set of word lines and the second set of word lines from the third set of word lines and the fourth set of word lines, wherein the at least one separation layer is parallel to both a digit line and a word line; and a plurality of storage elements each formed in a respective one of a plurality of recesses such that a respective storage element is surrounded by a respective word line, a respective digit line, respective dielectric layers, and a conformal material formed on a sidewall of a word line facing a digit line.

Vertical 3D memory device and method for manufacturing the same

Methods, systems, and devices for decoding architecture for memory tiles are described. Word line tiles of a memory array may each include multiple word line plates, which may each include a sheet of conductive material that includes a first portion extending in a first direction within a plane along with multiple fingers extending in a second direction within the plane. A pillar tile may include one or more pillars that extend vertically between the word line plate fingers. Memory cells may each be couple with a respective word line plate finger and a respective pillar. Word line decoding circuitry, pillar decoding circuitry, or both, may be located beneath the memory array and in some cases may be shared between adjacent pillar tiles.

Decoding architecture for memory tiles

Methods, systems, and devices for word line structures for three-dimensional memory arrays are described. A memory device may include word line structures that support accessing memory cells arranged in a three-dimensional level architecture. The word line structures may be arranged above a substrate and be separated from each other by respective dielectric layers. Each word line structure may include word line members and a word line plate that is connected to each word line member. Each word line plate may include a contact that may be coupled with a word line decoder operable to bias the word line plate. To couple the word line plate to the word line decoder, the memory device may include first vias that extend through holes in the word line plates and are coupled with second vias that extend from a respective contact through openings in the word line plates above the contact.

Word line structures for three-dimensional memory arrays

Methods, systems, and devices for decoding for a memory device are described. A decoder of a memory device may include transistors in a first layer between a memory array and a second layer that includes one or more components associated with the memory array. The second layer may include CMOS pre-decoding circuitry, among other components. The decoder may include CMOS transistors in the first layer. The CMOS transistors may control which voltage source is coupled with an access line based on a gate voltage applied to a p-type transistor and a n-type transistor. For example, a first gate voltage applied to a p-type transistor may couple a source node with the access line and bias the access line to a source voltage. A second gate voltage applied to the n-type transistor may couple a ground node with the access line and bias the access line to a ground voltage.

Decoding for a memory device

Methods, systems, and devices related to techniques to access a self-selecting memory device are described. A self-selecting memory cell may store one or more bits of data represented by different threshold voltages of the self-selecting memory cell. A programming pulse may be varied to establish the different threshold voltages by modifying one or more time durations during which a fixed level of voltage or current is maintained across the self-selecting memory cell. The self-selecting memory cell may include a chalcogenide alloy. A non-uniform distribution of an element in the chalcogenide alloy may determine a particular threshold voltage of the self-selecting memory cell. The shape of the programming pulse may be configured to modify a distribution of the element in the chalcogenide alloy based on a desired logic state of the self-selecting memory cell.

Techniques to access a self-selecting memory device

Methods, systems, and devices for voltage equalization for pillars of a memory array are described. In some examples, a memory array may be configured with conductive pillars that are each coupled with a respective set of memory cells, and may be selectively coupled with an access line. To support a dissipation or equalization of charge from unselected pillars, the memory array may be configured with a material layer or level that provides a dissipative coupling, such as a coupling having a relatively high resistance or a degree of capacitance, with a ground voltage or other voltage source (e.g., to support a passive equalization). Additionally, or alternatively, a memory array may be configured to support an active dissipation of accumulated charge or voltage by selectively coupling pillars that have been operated in a floating condition with a ground voltage or other voltage source (e.g., to perform a dynamic equalization).

Voltage equalization for pillars of a memory array

Apparatuses and methods for implementing artificial synapses utilizing SSM cells. A leaky-integrate-and-fire circuit can provide a feedback signal to an SSM cell responsive to a threshold quantity of pulses being applied to the gate from the signal line. A resulting state of the SSM cell can be dependent on a time difference between a latest of the threshold quantity of pulses and an initial pulse of the feedback signal.

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Auburn Hills, MI, United States of America

Paolo Fantini