Nvidia Corporation

Webtv Networks, Inc.

Other

Sun Microsystems, Inc.

Paolo Enrique Sabella

David B Kirk

John Erik Lindholm

Simon S Moy

Douglas A Voorhies

Matthew Nicholas Papakipos

John Stephen Montrym

Nicholas J Foskett

Kevin Dawallu

Mingjian Yang

Lincoln G Garlick

Jonah Matthew Alben

Stephen Donald Lew

Adrian Sfarti

Dennis K Ma

Mei-Chi M Liu

Samuel Hammond Duncan

James M Van Dyke

Nicholas P Wilt

John M Danskin

David William Nuechterlein

Edward Colton Greene

Robert Laker

Adam Malamy

Jeffrey M Smith

Shail Dave

Edouard Landau

Jerome Francis Duluk, Jr

Henry Packard Moreton

Mark J Kilgard

Sean Jeffrey Treichler

Wei-Je Robert Huang

Douglas H Rogers

Jerald R Evans

Richard A Silkebakken

Deron D Johnson

Robert J Hasslen

Shaun Ho

Nicholas M Baker

Daniel Cory Rohrer

Prakash G Apte

Nicholas P Witt

Charles M Flaig

Vikramjeet Singh

Methods, apparatuses, and systems are presented for performing asynchronous communications involving using an asynchronous interface to send signals between a source device and a plurality of client devices, the source device and the plurality of client devices being part of a processing unit capable of performing graphics operations, the source device being coupled to the plurality of client devices using the asynchronous interface, wherein the asynchronous interface includes at least one request signal, at least one address signal, at least one acknowledge signal, and at least one data signal, and wherein the asynchronous interface operates in accordance with at least one programmable timing characteristic associated with the source device.

Asynchronous interface for communicating between clock domains

An integrated circuit includes at least two different types of processors, such as a graphics processor and a video processor. At least one operation is commonly by supported by two different types of processors. For each commonly supported operation that is scheduled, a decision is made to determine which type of processor will be selected to implement the operation.

Apparatus, system, and method for distributing work to integrated heterogeneous processors

A processor having multiple independent engines can concurrently support a number of independent processes or operation contexts. The processor can independently schedule instructions for execution by the engines. The processor can independently switch the operation context that an engine supports. The processor can maintain the integrity of the operations performed and data processed by each engine during a context switch by controlling the manner in which the engine transitions from one operation context to the next. The processor can wait for the engine to complete processing of pipelined instructions of a first context before switching to another context, or the processor can halt the operation of the engine in the midst of one or more instructions to allow the engine to execute instructions corresponding to another context. The processor can affirmatively verify completion of tasks for a specific operation context.

Method and apparatus for context switching of multiple engines

A push buffer-related system, method and computer program product are provided. Initially, an entry is obtained from a buffer storage describing a size and location of a portion of a push buffer. To this end, the portion of the push buffer is capable of being retrieved, utilizing the entry from the buffer storage.

System and method for low-overhead push buffer jumps

An apparatus and method for servicing multiple graphics processing channels are described. In one embodiment, a graphics processing apparatus includes a scheduler configured to direct servicing of a graphics processing channel by issuing an index related to the graphics processing channel. The graphics processing apparatus also includes a processing core connected to the scheduler. The processing core is configured to service the graphics processing channel by: (i) correlating the index with a memory location at which an instance block for the graphics processing channel is stored; and (ii) accessing the instance block stored at the memory location.

Apparatus and method for servicing multiple graphics processing channels

Generally, the present disclosure concerns systems and methods for shadowing status for a circuit with a shadow unit. In one aspect, a system comprises a first circuit in a first dynamic clock domain of a plurality of dynamic clock domains, a processor configured to execute software instructions to generate a request for a status of the first circuit, and a second circuit coupled to the first circuit and to the processor. The second circuit, outside the first dynamic clock domain, is configured to shadow a status of the first circuit and to respond to the request for the status of the first circuit with the shadowed status.

Shadow unit for shadowing circuit status

An integrated circuit includes at least two different types of processors. At least one operation is supported by both types of processors, which permits a commonly supported operation to be scheduled on either processor.

Apparatus, system, and method for integrated heterogeneous processors

In one embodiment of the present invention, a GPU contains an authentication module at the front end, and a memory security engine and graphic memory interface at the backend. In one embodiment of the present invention, the memory security engine provides a privilege table. The programmable privilege table maps memory address ranges, and user IDs to privileges for accessing the memory address ranges. In one embodiment of the present invention, the memory security engine receives a memory access command along with an associated authenticated user ID. In one embodiment of the present invention, the memory security engine checks the authenticated user ID and address range against the privilege table. In one embodiment of the present invention, if the table indicates that the user has authorization for the particular read or write transaction to the graphic memory, the instruction is executed by the graphic memory interface. If the accessed address is not in the table, no special privileges are needed to access that address. If the table indicates that the user does not have authorization for the particular read or write transaction, the memory security engine provides a memory redirect.

Memory redirect primitive for a secure graphics processing unit

Software can freeze portions of a pipeline operation in a processor by asserting a predetermined freeze register in the processor. The processor halts operations relating to portions of a common pipeline processing in response to an asserted freeze register. Processor resources that operate downstream from the common pipeline continue to process any scheduled instructions. The processor is prevented from initiating any context switching in which a processor resource is allocated to a different channel. The processor stops supplying any additional data to downstream resources and ensures that the interface to downstream resources is clear of previously sent data. The processor prevents state machines from making additional requests. The processor asserts an acknowledgement indication in response to the freeze assertion when the processing has reached a stable state. Software is allowed to manipulate states and registers within the processor. Clearing the freeze register allows processing to resume.

Indicating acknowledge of stable state of pipeline resource when freeze bit set and context switch inhibited

An integrated circuit includes at least two different types of processors. The integrated circuit includes an integrated host and associated scheduler. At least one operation is supported by two or more different types of processors. The scheduler schedules operations on the different types of processors.

Apparatus, system, and method for integrated heterogeneous processors with integrated scheduler

Tile buffers in a graphics processing system are managed using 'copy-on-write' semantics, in which tile data stored in a memory location is not transferred to another location until the tile data for one of the buffers is modified, thereby providing copy on flip behavior to support incremental updating of the data. Tile data for a new frame is written to one of the two memory spaces by reference to a first logical buffer that associates each tile with one of the memory spaces. Concurrently, tile data for a current frame is read from the two memory spaces by reference to a second logical buffer that also associates each tile with one of the memory spaces. In response to a frame flip signal, the tile associations of the second logical buffer are modified to match those of the first logical buffer. Subsequent tile data updates are written to the memory spaces by reference to the second logical buffer after modifying one of the first and second tile associations such that they no longer match.

Incremental updating of animated displays using copy-on-write semantics

A system and method for pipelining three-dimensional graphical data in which two-dimensional renderings of objects are created from polygon data by transforming and lighting each polygonal vertex and then connecting the vertices.

System and method for organizing data for a 3-dimensional graphics pipeline

A system and method are provided for a hardware implementation of a blending technique during graphics processing in a graphics pipeline. During processing in the pipeline, a plurality of matrices and a plurality of weight values are received. Also received is vertex data to be processed. A sum of a plurality of products may then be calculated by the multiplication of the vertex data, one of the matrices, and at least one of the weights.

Blending system and method in an integrated computer graphics pipeline

A graphics pipeline system and method are provided for graphics processing. Such system includes a transform module positioned on a single semiconductor platform for transforming graphics data from object space to screen space. Coupled to the transform module is a lighting module which is positioned on the single semiconductor platform for lighting the graphics data. Also included is a rasterizer coupled to the lighting module and positioned on the single semiconductor platform for rendering the graphics data.

Single semiconductor graphics platform

Growing community of inventors

Pleasanton, CA, United States of America

Paolo Enrique Sabella