Apple Inc.

Paolo Di Febbo

Chaminda Nalaka Vidanagamachchi

Yohan Rajan

Anthony Ghannoum

Waleed Abdulla

Mohammad Ghasemzadeh

Anselm Grundhoefer

Mohamed Hassan Abu-Rahma

Yildiz Sinangil

Jelam K Parekh

Michele Stoppa

Kiranjit Dhaliwal

An apparatus includes an in-memory compute circuit that includes a memory circuit configured to generate a set of products by combining received input values with respective weight values stored in rows of the memory circuit, and to combine the set of products to generate an accumulated output value. The in-memory compute circuit may further include a control circuit and a plurality of routing circuits, including a first routing circuit coupled to a first set of rows of the memory circuit. The control circuit may be configured to cause the first routing circuit to route groups of input values to different ones of the first set of rows over a plurality of clock cycles, and the memory circuit to generate, on a clock cycle following the plurality of clock cycles, a particular accumulated output value that is computed based on the routed groups of input values.

Acceleration of in-memory-compute arrays

An apparatus includes a primary camera sensor configured to capture images having a first resolution, a primary processing circuit configured to process images captured by the primary camera sensor, a secondary camera sensor configured to capture images having a second resolution, and a secondary processing circuit configured to process images captured by the secondary camera sensor. In response to a determination that a particular object of interest is included in a particular image, the secondary processing circuit may be further configured to cause the primary processing circuit and the primary camera sensor to exit a reduced power mode. The primary camera sensor may be further configured, in response to the exiting, to capture a different image. The primary processing circuit may also be configured to process the different image to validate the particular object of interest.

Video monitoring using a hierarchical combination of camera sensors

Embodiments relate to a neural processor circuit that may include a fetch circuit that fetches coefficient data of a machine learning model from a memory source. The neural processor circuit may also include one or more neural engine circuits that are coupled to the fetch circuit. A neural engine circuit may include a buffer circuit that stores the coefficient data. The neural engine circuit may also include a coefficient organizing circuit that generates at least a first mapping and a second mapping of the stored coefficient data according to one or more control signals. The neural engine may also include a computation circuit that receives and processes at least a portion of input data with the coefficient data as mapped according to the first mapping or process at least the portion of the input data with the coefficient data as mapped according to the second mapping.

Mappable filter for neural processor circuit

In an embodiment, a local memory dedicated to one or more hardware accelerators in a system may include at least two portions: a volatile portion and a non-volatile portion. Data that is reused from iteration to iteration of the hardware accelerator (e.g. constants, instruction words, etc.) may be stored in the non-volatile portion. Data that varies from iteration to iteration may be stored in the volatile portion. Both the local memory and the hardware accelerators may be powered down between iterations, saving power. The non-volatile portion need only be initialized at a first iteration, allowing the amount of time that the hardware accelerators and the local memory are powered up to be lessened for subsequent iterations since the reused data need not be reloaded in the subsequent iterations.

Hybrid memory in a dynamically power gated hardware accelerator

Embodiments relate to an electronic device that includes a neural processor having multiple neural engine circuits that operate in multiple modes of different bit width. A neural engine circuit may include a first multiply circuit and a second multiply circuit. The first and second multiply circuits may be combined to work as a part of a combined computation circuit. In a first mode, the first multiply circuit generates first output data of a first bit width by multiplying first input data with a first kernel coefficient. The second multiply circuit generates second output data of the first bit width by multiplying second input data with a second kernel coefficient. In a second mode, the combined computation circuit generates third output data of a second bit width by multiplying third input data with a third kernel coefficient.

Dynamic variable bit width neural processor

A tracked device may be used in an extended reality system in coordination with a tracking device. The tracked device may be ordinarily difficult to track, for example due to changing appearances or relatively small surface areas of unchanging features, as may be the case with an electronic device with a relatively large display surrounded by a thin physical outer boundary. In these cases, the tracked device may periodically present an image to the tracking device that the tracking device stores as an indication to permit tracking of a known, unchanging feature despite the image not being presented continuously on the display of the tracked device. The image may include a static image, designated tracking data overlaid on an image frame otherwise scheduled for presentation, or extracted image features from the image frame otherwise scheduled for presentation. Additional power saving methods and known marker generation methods are also described.

Display tracking systems and methods

Various implementations disclosed herein include multi-scale visual markers that convey information in multiple sets of markings using different respective appearance attributes. In some implementations, the appearance attribute of the markings of a first set of markings corresponds to a first encoding parameter and the appearance attribute of markings of a second set of markings corresponds to a second encoding parameter different from the first encoding parameter. In some implementations, the first set of markings encode first data and the second set of markings are different than the first set of markings and encode second data. In some implementations, the different appearance attributes are different scales (e.g., different sizes, different numbers of markings per unit of space, different contrast, different color characteristics, different wavelengths, different image sensor types, etc.).

Visual marker

In an embodiment, a local memory that is dedicated to one or more hardware accelerators is divided into a plurality of independently powerable sections. That is, one or more of the sections may be powered on while other ones of the plurality of sections are powered off. The hardware accelerators receive instruction words from one or more central processing units (CPUs). The instruction words may include a field that specifies an amount of the memory that is used when processing the first instruction word, and the power control circuit may be configured to power a subset of the plurality of sections to provide sufficient memory for the instruction word based on the field, while one or more of the plurality of sections are powered off.

Growing community of inventors

Redwood City, CA, United States of America

Paolo Di Febbo