Credence Systems Corporation

Schlumberger Technologies, Inc.

Paolo Dalla Ricca

Burnell G West

Moussa Najib Iskandar

Daniel Rosenthal

Maurizio Gavardoni

Peter Cockburn

A programmable source/measurement module for automatic test equipment is disclosed. A high resolution low frequency source, high resolution low frequency measurement capability, low resolution high frequency source, and a low resolution high frequency measurement capability are provided in a single module. The module comprises an input/output switch matrix selectively coupled to a low frequency filter block and a high frequency filter block. Each filter block may be used for either source or measurement. The filter blocks are selectively coupled to a plurality of analog-to-digital converters (ADCs) and digital-to-analog converters (DACs). The ADCs and DACs are coupled to a digital interface.

Programmable multi-function module for automatic test equipment systems

A method and apparatus for adding fill-in clock pulses to an analog to digital converters input clock signal between requests for analog data acquisition. The circuit that provides the fill-in clock pulses is able to detect a request for analog data acquisition, synchronously stop adding fill-in clock pulses, and track the request for data acquisition.

Method and apparatus for use of high sampling frequency A/D converters for low frequency sampling

Generating test signals for a device under test (DUT) involves generating a master reference signal, using a vernier technique to generate test pattern signals based on the master reference signal, generating a test clock signal that is phase-matched with and frequency similar to the test pattern signals by providing the master reference signal as input to a phase-locked loop (PLL) and controlling one or more programmable dividers in the PLL to adjust the test clock signal to be a multiple or sub-multiple of a frequency of the test pattern signals, applying the test clock signal to the clock input pin of the DUT, and applying the test pattern signals to data pins of the DUT. When the frequency of the test pattern signals is changed, the test clock signal frequency may be adjusted to calibrate to the changed frequency of the test pattern signals by re-programming the programmable dividers.

Low-jitter clock for test system

An analog test instrument used in an apparatus for testing electronic devices has multiple analog modules for supplying test signals to analog pins of a device under test and receiving response signals from the analog pins. The analog modules may be of the same type or of different types. The analog test instrument also has programmable devices that control in an independent manner the triggering, clocking, and generation of the test signals supplied by each of the analog modules, so that test signals of various timings, speeds and waveforms may be generated.

Test instrument with multiple analog modules

A method simulating the filtering of a current pulse in a series of pulses. The method includes receiving a series of n+1 consecutive pulse addresses, including a pulse address for the current pulse as the last in the series of n+1, each pulse address being in a range of m values; storing the n pulses addresses prior to the current pulse address; building a composite address from the current pulse address and the prior n pulse addresses and applying the composite address to read a pulse shape from a memory of at least m.sup.n+1 pulse shapes. Also, apparatus issuing high speed pulses of programmable length. The apparatus includes a field of programmable memory to store a pulse length; a pulse clock line carrying a pulse clock signal having a pulse frequency; a frequency multiplier connected to receive the pulse clock signal and the pulse length stored in the programmable memory field and producing a sample clock signal having a frequency equal to the pulse length times the pulse clock frequency; a pulse memory holding the samples for a pulse; a DAC coupled to the pulse memory and generating analog pulses from samples received from the pulse memory; and a signal path carrying the sample clock signal to set the sampling frequency of a DAC and to clock samples from the pulse memory to the DAC.

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Fremont, CA, United States of America

Paolo Dalla Ricca