Stmicroelectronics S.r.l.

Sgs-thomson Microelectronics S.r.l.

Paolo Cusinato

Andrea Baschirotto

Gabriele Gandolfi

Vittorio Colonna

Melchiorre Bruccoleri

Davide Tonietto

Rinaldo Castello

Fabio Pasolini

Giampiero Montagna

Vlttorio Colonna

The amplifier circuit includes at least one amplification branch having an input transistor, an output transistor, having a source terminal connected to the input terminal and a drain terminal connected to a first output terminal, and a gain raising stage, having an input and an output connected to the source terminal and, respectively, to a gate terminal of the output transistor. The amplifier circuit includes, moreover, a compensation capacitor connected between the gate terminal and the drain terminal of the output transistor.

Class AB operational amplifier having high gain and low settling time

A method of improving the signal/noise ratio of a sigma-delta modulator during the re-establishment of its stability that includes: defining a bit sequence corresponding to a state of instability of the modulator, monitoring the flow of bits output by the modulator to check whether it contains the instability bit sequence, and resetting the modulator to zero if the instability bit sequence is detected at the output. To ensure a high signal/noise ratio of the modulator even during the detection and re-establishment of stability, the method also includes: delaying the flow of bits output by the modulator at least for the time required to detect the instability bit sequence and modifying the output bit sequence during the delay period by replacing it with a predetermined bit sequence.

Method and circuit for improving the signal/noise ratio of a sigma-delta modulator

Fully differential operational amplifier of the folded cascode type

A method of re-establishing the stability of a sigma-delta modulator having a plurality of integrator stages in cascade and a quantizer, achieving very short resetting times, a bit sequence corresponding to an instability state of the modulator is defined, the bit-stream output by the modulator is monitored to check whether it includes the instability sequence and, if the instability sequence is detected, the last integrator stage is reset and one or more preceding integrator stages are reset, progressively, until the instability sequence is no longer detected.

Method of re-establishing the stability of a sigma-delta modulator and a circuit for implementing the method

A class AB single-stage operational amplifier having input decoupler stages for voltage signals, a voltage repeater stage, biasing transistors and bias current generators for the input decoupler stages, and capacitors placed between the input decoupler stages and the voltage repeater stage so as to increase the phase margin.

Class AB single-range advanced operational amplifier

Digital-analog converter comprising a third order sigma delta modulator

Fully-differential, switched-capacitor circuit having a first and second input terminal, and including: an operational amplifier having a first and a second differential input, a first and a second output terminal and a bias control terminal; a feedback network, connected between the differential outputs and the input terminals, and having intermediate nodes connected to the differential inputs of the operational amplifier; and a control circuit, including a detection network and an error amplifier. The error amplifier has a first input receiving a desired common-mode voltage, and an output connected to the bias control terminal and supplying a control voltage. The detection network has a first and a second input connected directly, respectively, to the second input terminal of the operational amplifier, and an output connected to a second input of the error amplifier, and supplying a common-mode drive voltage.

Switched-capacitor, fully-differential operational amplifier with high switching frequency

A switched operational amplifier with fully differential topology, alternately switchable on and off, and a control circuit. The operational amplifier has a first differential output ( ) and a second differential output, and a control terminal. The control circuit includes a capacitive detecting network including a first capacitor and a second capacitor connected between the first and second differential outputs and a common-mode node, and a third capacitor connected between the common-mode node and ground in a first operative condition, and between the common-mode node and the supply voltage in a second operative condition. A control transistor is connected between the common-mode node and the control terminal of the operational amplifier and supplies a control current correlated to the voltage on the common-mode node. A switchable voltage source, connected to the common-mode node, supplies a desired voltage in a first operative condition, when the operational amplifier is off.

Fully differential, switched capacitor, operational amplifier circuit with common-mode controlled output

Current generator for alternatively providing a first constant current and a ratioed second constant current to a sigma-delta modulator

The invention relates to a Class AB operational amplifier providing both output gain enhancement and adaptative output bias. The operational amplifier includes first and second output terminals; a main differential stage having first and second differential inputs and a first differential output stage; a first adaptatively biased, boosted output stage coupling the first differential output stage to the output terminal. Each output stage includes a first NMOS output transistor having a control terminal, a first terminal coupled to the respective output terminal, and a second terminal, and includes a first output amplifier having a first input coupled to the second terminal of the first output transistor, a second input coupled to the first differential output stage to provide adaptative bias for the first boosted output stage, and an output coupled to the control terminal of the first output transistor.

Operational amplifier with enhanced-gain output stages

An integrated circuit has a first external supply terminal and a second external supply terminal for applying an external supply voltage to the circuit. The integrated circuit includes an analog unit supplied by at least one internal supply voltage derived from the external supply voltage, a low-pass filter connected to the first external supply terminal and to the second external supply terminal, and a driver connected between the low-pass filter and the analog unit for supplying the at least one internal supply voltage.

Integrated structure with an analog unit supplied by an external supply voltage by means of a low-pass filter and driving elements

An analog/digital &Sgr;&Dgr; converter has an input fed with an analog input signal, an output producing a digital signal representative of the analog input signal and a circuit for generating a dithering signal of amplitude adaptively regulated depending on the amplitude of the analog input signal. A comparator performs the regulation and uses a white noise dithering signal that is digitally generated and thereafter converted into an analog white noise dithering signal subjected to a second order filtering.

Sigma-delta analog/digital converter with adaptive dither

A timed bistable circuit is described which includes two inverters each having its input connected to the output of the other, an output of the circuit via a &ldquo;buffer&rdquo; and an input of the circuit via a controlled electronic switch. The supply terminals of the inverters are connected to the supply terminals of the circuit via another two controlled switches. A clock generator provides timing signals to control both the input switches to open or close and to control the supply switches to close or open when the input switches are open or closed respectively. To obtain a latch usable in a comparator at a high comparison frequency the offset referred to the input is reduced and made independent of the frequency by arranging two further electronic switches between the supply terminals of the inverters and the supply terminals which are controlled by a timing signal in such a way as to close with a predetermined delay with respect to the closure of the input switches and to open when input switches open.

Timed bistable circuit for high frequency applications

A voltage-controlled oscillator, with high noise rejection of the supply voltage, includes a plurality of delay cells in an odd number N.gtoreq.3, which are connected to form a first ring oscillator and powered by the difference between a supply voltage Vcc and a variable regulating voltage VR. The VCO comprises at least one second ring oscillator formed by a plurality of delay cells in an odd number M.gtoreq.3, at least one of which is also a delay cell of the first oscillator and at least two of which do not belong to the first oscillator. At least one of these two cells is powered by a constant voltage (Vcc), in such a manner that the two oscillators operate at the same frequency and the interaction between the two oscillators introduces a high-frequency negative feedback which has the effect of effectively reducing the noise of the supply voltage Vcc.

VCO composed of plural ring oscillators and phase lock loop

A timed bistable circuit is described which includes two inverters each having its input connected to the output of the other, an output of the circuit via a 'buffer' and an input of the circuit via a controlled electronic switch. The supply terminals of the inverters are connected to the supply terminals of the circuit via another two controlled switches. A clock generator provides timing signals to control both the input switches to open or close and to control the supply switches to close or open when the input switches are open or closed respectively. To obtain a latch usable in a comparator at a high comparison frequency the offset referred to the input is reduced and made independent of the frequency by arranging two further electronic switches between the supply terminals of the inverters and the supply terminals which are controlled by a timing signal in such a way as to close with a predetermined delay with respect to the closure of the input switches and to open when input switches open.

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Sestri Levante, Italy

Paolo Cusinato