Stmicroelectronics S.r.l.

Paolino Schillaci

Salvatore Poli

Antonino La Malfa

Maurizio Francesco Perroni

Salvatore Polizzi

Antonio Giambartino

Salvatore Mazzara

Slavatore Polizzi

A synchronous non-volatile memory device that includes a circuit for performing operations on the memory device, a circuit for receiving a request of operation and operative information required for performing the operation in temporal succession, an activation circuit for activating the circuit in response to the request of operation, a circuit for enabling the execution of the operation in response to the operative information, and a deactivation circuit for deactivating the operations performing circuit in response to the completion of the operation.

Synchronous memory device with reduced power consumption

The invention relates to an automatic decoding method for mapping and selecting a non-volatile memory device having a LPC serial communication interface in the available addressing area on motherboards. A logic structure is incorporated in the memory device, which allows a correct decoding to address the memory to the top of the addressable area or to the bottom of the same area, i.e., in both possible cases. This logic incorporates a non-volatile register whose information is stored in a Content Address Memory to enable the automatic mapping of the memory in the addressable memory area.

Automatic decoding method for mapping and selecting a non-volatile memory device having a LPC serial communication interface in the available addressing area on motherboards

The present invention relates to a non volatile memory device architecture, for example of the Flash type, incorporating a memory cell array and an input/output interface to receive memory data and/or addresses from and to the outside of the device. The interface operates generally according to a serial communication protocol, but it is equipped with a further pseudo-parallel communication portion with a low pin number incorporating circuit blocks for selecting the one or the other communication mode against an input-received selection signal.

Non-volatile memory device architecture, for instance a flash kind, having a serial communication interface

The invention provides a protocol cycle during which a memory address and all the data bytes to be written are transmitted, and the writing process is carried out only once for all the transmitted data bytes, by writing a first byte in the memory sector corresponding to a first address generated by resetting to zero the 2 least significant bits of the transmitted address and all the other transmitted bytes in successive addresses. The method includes writing a certain number N of data bytes, in consecutive memory addresses in a memory array of a memory device, and includes unprotecting the memory sectors in which data are to be written, communicating the programming command to the memory device, communicating to the memory device the bits to be stored and specifying a relative memory address of a sector to write in, and writing the data bits in the memory.

Method of writing a group of data bytes in a memory and memory device

An electronic circuit structure for updating a block of memory cells in a flash memory device, the memory cells storing a current value, wherein the structure includes a data latch for receiving a new value to be written on the memory cells, a controller for erasing the block of memory cells simultaneously, and programming load bank coupled to the controller and the data latch for programming the memory cells individually; the structure further includes control logic coupled to the controller for enabling the controller and for enabling the programming load bank according to a comparison between the new value and the current value.

Structure for updating a block of memory cells in a flash memory device with erase and program operation reduction

A circuit architecture and a method perform a page programming in non-volatile memory electronic devices equipped with a memory cell matrix and an SPI serial communication interface, as well as circuit portions associated to the cell matrix and responsible for the addressing, decoding, reading, writing and erasing of the memory cell content. Advantageously, a buffer memory bank is provided to store and output data during the page programming in the pseudo-serial mode through the interface. Data latching is performed one bit at a time and the following outputting occurs instead with at least two bytes at a time.

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Casteltermini, Italy

Paolino Schillaci