Stmicroelectronics S.r.l.

Sgs-thomson Microelectronics S.r.l.

Paola Paruzzi

Federico Pio

Bruno Vajana

Livio Baldi

Alberto Modelli

Enrico Gomiero

A generator for generating a plurality of predetermined voltage values for non-volatile memories. The generator includes an input node, a plurality of circuit branches, and an output terminal. The input node has a reference voltage and is connected to at least one of the circuit branches. Each of the circuit branches has at least one active element to selectively and independently turn on and turn off each of the circuit branches by a voltage applied to a control terminal of each active element. The output terminal connects to at least one of the circuit branches and supplies a voltage level based on the reference voltage and a voltage drop across each activated circuit branch. Alternatively, the output terminal supplies a floating voltage level in the event of one or more of the active elements along each of the circuit branches being turned off so as to isolate the input node from the output terminal.

Monolithically integrated generator of a plurality of voltage values

A test structure is formed by an array of memory cells connected in parallel and including each a memory transistor and a select transistor connected in series. The gate terminals of the select transistors of all memory cells are biased to a value next to the threshold voltage of the select transistors. Therefore, in each memory cell, the drain current is limited by the memory transistor for control gate voltages below the threshold voltage of the memory transistor, and by the select transistor at higher voltages; for high control gate voltages, the drain current is clamped to a constant maximum value. Since the clamping effect of the select transistors acts on each memory cell, the total maximum current of the test structure may be held below a value causing a limitation in the current generated by the entire array because of the resistance in series to the output of the test structure. Thus also the right side of the threshold distribution may be evaluated and the presence of defective cells causing injection of electrons in the floating gate of the memory transistors may be detected.

Nonvolatile memory test structure and nonvolatile memory reliability

The present invention concerns an electrically programmable and erasable non-volatile memory cell having a traditional structure but being inverted in the conductivity type of the component elements and lacking the second source diffusion.

P-channel memory cell and method for forming the same

A matrix of EEPROM memory cells having a double polysilicon level of MOS technology and being arranged into rows and columns is monolithically integrated on a substrate of semiconductor material. Each cell comprises, in series, a transistor of the floating gate type which includes two layers of polysilicon superposed on each other and separated by an intervening layer of a dielectric material, and a selection transistor having a gate which comprises a first layer of polysilicon. The gates of the selection transistors in one row of said matrix are connected electrically together by a selection line comprising a second layer of polysilicon overlying the first layer. The intermediate layer of dielectric material is also partly interposed between the first and second layers of polysilicon such that the two layers are in contact at at least one zone of said selection line. Preferably, the contact zone is formed over field oxide regions and is away from the edges of the selection line. The matrix can advantageously be fabricated by a process of the self-aligned type, without making the process any more complicated.

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Robbiate, Italy

Paola Paruzzi