Sgs-thomson Microelectronics S.r.l.

Stmicroelectronics S.r.l.

Sgs Microelettronica Spa

Sgs-thomson Microelectronics, 2 Via C. Olivetti

Paola Galbiati

Claudio Contiero

Antonio Andreini

Michele Palmieri

Lucia Zullino

Ubaldo Mastromatteo

Alessandra Merlini

Domenico Rossi

Carlo Cini

Franco Bertotti

Giorgio Pedrazzini

Massimo Pozzoni

Alessandro Moscatelli

Giuseppe Croce

Luca Bertolini

Paolo Cordini

Lorenzo Cerati

Riccardo De Petro

Luica Zullino

Lodovica Vecchi

A semiconductor electronic device is described comprising a die of semiconductor material having a plurality of contact pads electrically connected to a support for example through interposition of contact wires, said plurality of contact pads comprising signal pads and power pads, the device being characterized in that said signal pads are implemented on the die of semiconductor material with a mutual pitch lower than the pitch between said power pads.

Semiconductor electronic device and method of manufacturing thereof

An LDMOS structure is formed in a region of a first type of conductivity of a semiconductor substrate and comprises a gate, a drain region and a source region. The source region is formed by a body diffusion of a second type of conductivity within the first region, and a source diffusion of the first type of conductivity is within the body diffusion. An electrical connection diffusion of the second type of conductivity is a limited area of the source region, and extends through the source diffusion and reaches down to the body diffusion. At least one source contact is on the source diffusion and the electrical connection diffusion. The LDMOS structure further comprises a layer of silicide over the whole area of the source region short-circuiting the source diffusion and the electrical connection diffusion. The source contact is formed on the silicide layer.

Low on-resistance LDMOS

Complementary LDMOS and MOS structures and vertical PNP transistors capable of withstanding a relatively high voltage may be realized in a mixed-technology integrated circuit of the so-called &ldquo;smart power&rdquo; type, by forming a phosphorus doped n-region of a similar diffusion profile, respectively in: The drain zone of the n-channel LDMOS transistors, in the body zone of the p-channel LDMOS transistors forming first CMOS structures; in the drain zone of n-channel MOS transistors belonging to second CMOS structures and in a base region near the emitter region of isolated collector, vertical PNP transistors, thus simultaneously achieving the result of increasing the voltage withstanding ability of all these monolithically integrated structures. The complementary LDMOS structures may be used either as power structures having a reduced conduction resistance or may be used for realizing CMOS stages capable of operating at a relatively high voltage (of about 20V) thus permitting a direct interfacing with VDMOS power devices without requiring any &ldquo;level shifting&rdquo; stages. The whole integrated circuit has less interfacing problems and improved electrical and reliability characteristics.

Mixed technology integrated device comprising complementary LDMOS power transistors, CMOS and vertical PNP integrated structures having an enhanced ability to withstand a relatively high supply voltage

In a junction isolated integrated circuit including power DMOS transistors formed in respective well regions or in an isolated epitaxial region on a substrate of opposite type of conductivity, circuits are formed in a distinct isolated region sensitive to oversupply and/or belowground effects. These effects are caused by respective power DMOS transistors coupled to the supply rail or ground. These effects are alternatively controllable by specifically shaped layout arrangements, and may be effectively protected from both effects. This is achieved by interposing between the region of sensitive circuits and the region containing the power DMOS transistors for which the alternatively implementable circuital arrangements are not formed, the region containing the power DMOS transistors coupled to the supply rail or to a ground rail for which the alternatively implementable arrangements are formed. The special interposition separates and shields the sensitive circuits from the power device whose oversupply or belowground effect is not countered by specific circuit arrangements.

Belowground and oversupply protection of junction isolated integrated circuits

A high-voltage lateral MOSFET transistor structure constituted by various interdigitated modular elements formed on a layer of monocrystaline silicon is described together with a process for its fabrication. To save area of silicon and to reduce the specific resistivity RDS on doping drain regions are formed by implanting doping material in the silicon through apertures in the field oxide obtained with a selective anisotropic etching by utilizing as a mask the strips of polycrystaline silicon which serve as gate electrodes and field electrodes.

Process for fabricating a high voltage MOSFET

A process for the manufacturing of an integrated circuit having DMOS-technology power devices and non-volatile memory cells provides for forming respective laterally displaced isolated semiconductor regions, electrically insulated from each other and from a common semiconductor substrate, inside which the devices will be formed; forming conductive gate regions for the DMOS-technology power devices and for the memory cells over the respective isolated semiconductor regions. Inside the isolated semiconductor regions for the DMOS-technology power devices, channel regions extending under the insulated gate regions are formed. The channel regions are formed by an implantation of a dopant along directions tilted of a prescribed angle with respect to a direction orthogonal to a top surface of the integrated circuit, in a dose and with an energy such that the channel regions are formed directly after the implantation of the dopant without performing a thermal diffusion at a high temperature of the dopant.

Process for the manufacturing of integrated circuits comprising

A diode integrated on semiconductor material with BCD technology and of the type provided on a substrate having a first type of conductivity inside an isolation region having a second type of conductivity. The diode comprises also a buried anode region having a first type of conductivity and a cathode region having a second type of conductivity. The cathode region comprises an epitaxial layer located above the buried anode region and a highly doped region provided inside the epitaxial layer. The buried anode region comprises depressions opposite which is located the highly doped region with the depressions being achieved by the intersection of lateral diffusions of distinct and adjacent portions of the buried anode region.

Method for fabricating a semiconductor diode with BCD technology

A process for doping a P-type substrate (50) by forming a layer (52) of silicon nitride, implanting N-type impurities through this layer (FIG. 7), forming a resist mask (54) which leaves at least one area of the substrate (FIG. 8) containing a part of the nitride layer exposed, implanting N-type impurities first with an insufficient energy and then with a sufficient energy to traverse the nitride layer, subjecting (FIG. 9) the substrate to a high temperature treatment in an oxidizing environment to form silicon dioxide pads (55) on the areas of the substrate not covered by the nitride layer, removing the nitride layer and performing an implantation of P-type impurities into the areas delimited by the pads. The process then continues with the removal of the pads and, in the conventional manner, with the formation of an epitaxial layer and selective doping of this to form P-type and N-type regions in it. The process described allows the production of integrated devices with an additional buried layer while utilizing one fewer mask than conventional processes.

Process for the fabrication of semiconductor devices having various

Semiconductor diode integrated with bipolar/CMOS/DMOS technology

The breakdown voltage of a VDMOS transistor is markedly increased without depressing other electrical characteristics of the device by tying the potential of a field-isolation diffusion, formed under the edge portion of a strip of field oxide separating a matrix of source cells from a drain diffusion, to the source potential of the transistor. This may be achieved by extending a body region of a peripheral source cell every given number of peripheral cells facing the strip of field-isolation structure until it intersects said field-isolation diffusion. By so connecting one peripheral source cell every given number of cells, the actual decrement of the overall channel width of the integrated transistor is negligible, thus leaving unaltered the electrical characteristics of the power transistor.

Method for fabricating VDMOS transistor with improved breakdown

VDMOS transistor with improved breakdown characteristics

A high density, mixed technology integrated circuit comprises CMOS structures and bipolar lateral transistors, the electrical efficiency and Early voltage of which are maintained high by forming 'well' regions through the collector area. The operation determines the formation of a 'collector extension region' extending relatively deep within the epitaxial layer so as to intercept the emitter current and gather it to the collector, subtracting it from dispersion toward the substrate through the adjacent isolation junctions surrounding the region of the lateral bipolar transistor. Under comparable conditions, the ratio between IcIsubstrate is incremented from about 8 to about 300 and the Early voltage from about 20V to about 100V. The V.sub.CEO, BV.sub.CBO and BV.sub.CDES voltages are also advantageously increased by the presence of said 'well' region formed in the collector zone.

Mixed technology integrated circuit comprising CMOS structures and

Complementary LDMOS and MOS structures and vertical PNP transistors capable of withstanding a relatively high voltage may be realized in a mixed-technology integrated circuit of the so-called 'smart power' type, by forming a phosphorus doped n-region of a similar diffusion profile, respectively in: The drain zone of the n-channel LDMOS transistors, in the body zone of the p-channel LDMOS transistors forming first CMOS structures; in the drain zone of n-channel MOS transistors belonging to second CMOS structures and in a base region near the emitter region of isolated collector, vertical PNP transistors, thus simultaneously achieving the result of increasing the voltage withstanding ability of all these monolithically integrated structures. The complementary LDMOS structures may be used either as power structures having a reduced conduction resistance or may be used for realizing CMOS stages capable of operating at a relatively high voltage (of about 20V) thus permitting a direct interfacing with VDMOS power devices without requiring any 'level shifting' stages. The whole integrated circuit has less interfacing problems and improved electrical and reliability characteristics.

Mixed technology integrated device comprising complementary LDMOS power

This method, requiring a reduced number of process phases and providing an efficient, high-voltage structure, comprises forming a P-well region of the N-channel transistor of a CMOS device, by means of boron atom implant through a protective mask, forming at least one insulation region surrounding the CMOS device, forming edge regions having the same conductivity type as the insulation region but with a smaller concentration of impurities on at least one part of the insulation region and in the high-voltage electronic devices by means of the same boron atom implant used to form the P-well region.

Method for manufacturing semiconductor integrated circuits including

Disclosed is a monolithic integrated semiconductor device which may contain specimens of seven different circuit components; namely: lateral N-MOS and lateral P-MOS transistors (CMOS), vertical N-DMOS and vertical P-DMOS transistors, vertical NPN bipolar transistors, vertical PNP bipolar transistors with isolated collector and low leakage junction diodes as well as a process for fabricating such a device.

Growing community of inventors

Monza, Italy

Paola Galbiati