Advanced Semiconductor Engineering, Inc.

Pao-Nan Lee

Chang Chi Lee

Chien-Hua Chen

Chi-Han Chen

Jung Jui Kang

Teck-Chong Lee

Chi-Tsung Chiu

Chih-Pin Hung

Cheng-Yuan Kung

Hung-Yi Lin

Chen-Chao Wang

Yung-Shun Chang

Ying-Te Ou

Hung-Chun Kuo

Chun-Yen Ting

Ying-Chieh Shyu

Sheng-Chi Hsieh

Chi Tsung Chiu

Chin-Cheng Kuo

Hsin Hsiang Wang

Chiung-Ying Kuo

Chien Hua Chen

Min-Tzu Hsu

Po-Hao Chen

An electronic device is disclosed. The electronic device includes a carrier including a first region and a second region distinct from the first region. The electronic device also includes an electronic component covering the first region and at least partially exposing the second region. The electronic device also includes a first power regulating element in the second region of the carrier and a second power regulating element. The second power regulating element is disposed adjacent to the first power regulating element and electrically connected to the electronic component through the first power regulating element to provide a first power path.

Electronic device

An electronic device is provided. The electronic device includes a first die and a second die. The second die is disposed over the first die. A backside surface of the second die faces a backside surface of the first die. An active surface of the second die is configured to receive a first power. The second die is configured to provide the first die with a second power through the backside surface of the second die and the backside surface of the first die.

Electronic device including electronic component receiving power from two sides

An electronic device is disclosed. The electronic device includes a first electronic component and a power regulating structure configured to provide a first power to the first electronic component. The power regulating structure includes a first component and a second component at least partially overlapped with the first component from a top view.

Semiconductor package with integrated voltage regulator device and separate bridge die

An electronic device is disclosed. The electronic device includes a carrier including a first portion, a second portion over the first portion, and a third portion connecting the first portion and the second portion. The electronic device also includes a first electronic component disposed between the first portion and the second portion. An active surface of the first electronic component faces the second portion. The electronic device also includes a second electronic component disposed over the second portion. The first portion is configured to transmit a first power signal to a backside surface of the first electronic component opposite to the active surface.

A semiconductor package structure is provided. The semiconductor package structure includes an electronic component, and an inductance component. The protection layer encapsulates the electronic component and has a top surface and a bottom surface. The top surface and the bottom surface collectively define a space to accommodate the electronic component. The inductance component outflanks the space from the top surface and the bottom surface of the protection layer.

Semiconductor package structure

An electronic device is disclosed. The electronic device includes a system board and a first set of electronic devices disposed over the system board. Each of the first set of electronic devices comprises a processing unit and a carrier carrying the processing unit. The electronic device also includes a first interconnection structure electrically connected with the processing unit through the carrier and configured to receive a first power from a first power supply unit and to transmit the first power to the processing unit.

A capacitor bank structure includes a plurality of capacitors, a protection material, a first dielectric layer and a plurality of first pillars. The capacitors are disposed side by side. Each of the capacitors has a first surface and a second surface opposite to the first surface, and includes a plurality of first electrodes and a plurality of second electrodes. The first electrodes are disposed adjacent to the first surface for external connection, and the second electrodes are disposed adjacent to the second surface for external connection. The protection material covers the capacitors, sidewalls of the first electrodes and sidewalls of the second electrodes, and has a first surface corresponding to the first surface of the capacitor and a second surface corresponding to the second surface of the capacitor. The first dielectric layer is disposed on the first surface of the protection material, and defines a plurality of openings to expose the first electrodes. The first pillars are disposed in the openings of the first dielectric layer and protrude from the first dielectric layer.

Capacitor bank structure and semiconductor package structure

The present disclosure relates to a semiconductor package and a method of manufacturing the same. In some embodiments, a semiconductor package includes a substrate, at least one die, a sealing ring and an inductor. The at least one die is mounted on the substrate and includes a plurality of component structures operating with acoustic waves. The component structures are arranged on a side of the at least one die that faces the substrate. The sealing ring is disposed between the at least one die and the substrate and surrounds the component structures. The inductor is disposed in the substrate.

Semiconductor package and semiconductor process

In one or more embodiments, a semiconductor device includes a substrate, a first dielectric layer and a first conductive layer. The substrate includes a first surface and a second surface opposite the first surface. The first dielectric layer is on the first surface of the substrate. The first conductive layer is on the first surface of the substrate and includes a first portion on the first dielectric layer and a second portion surrounded by the first dielectric layer. The second portion of the first conductive layer extends from the first portion of the first conductive layer through the first dielectric layer to contact the first surface of the substrate.

Power and ground design for through-silicon via structure

The present disclosure relates to a semiconductor package structure and a method of manufacturing the same. The semiconductor package structure includes a semiconductor substrate having a first surface and a second surface opposite the first surface. The semiconductor substrate has a space extending from the second surface to the first surface and an insulation body is disposed in the space. The semiconductor package structure includes conductive posts in the insulation body.

Semiconductor package structure and method of manufacturing the same

A semiconductor device includes a substrate, a seed layer, a first patterned metal layer, a dielectric layer and a second metal layer. The seed layer is disposed on a surface of the substrate. The first patterned metal layer is disposed on the seed layer and has a first thickness. The first patterned metal layer includes a first part and a second part. The dielectric layer is disposed on the first part of the first patterned metal layer. The second metal layer is disposed on the dielectric layer and has a second thickness, where the first thickness is greater than the second thickness. The first part of the first patterned metal layer, the dielectric layer and the second metal layer form a capacitor. The first part of the first patterned metal layer is a lower electrode of the capacitor, and the second part of the first patterned metal layer is an inductor.

Semiconductor device and process of making the same

A semiconductor transformer includes a first coil inductor and a second coil inductor. The first coil inductor has a first port, a second port and a first coil inductor wall, the first coil inductor wall having a height substantially equal to a thickness of the substrate. The second coil inductor has a third port, a first extension wall connected to the third port, a fourth port, a second extension wall connected to the fourth port and a second coil inductor wall.

Semiconductor transformer device and method for manufacturing the same

A band pass filter includes an original circuit. An interaction of at least two of components of the original circuit produces at least a mutual capacitor or at least a mutual inductor, which constitutes a resonance circuit with the original circuit to produce at least a transmission zero for increasing the attenuation rate of the stop band.

Band pass filter

A circuit substrate including a laminated layer, an embedded electronic device, at least a circuit structure, and a solder mask layer is provided. The embedded electronic device is disposed within the laminated layer. The circuit structure is disposed on a surface of the laminated layer and is connected between a reference plane and the embedded electronic device. In addition, the solder mask layer is disposed on the surface of the laminated layer and exposes a portion of the circuit structure. The circuit structure has a specific layout by which a circuit trace with an adjustable length can be formed by disconnecting or connecting the exposed portion of the circuit structure.

Growing community of inventors

Kaohsiung, Taiwan

Pao-Nan Lee