Mediatek Corporation

Realtek Semiconductor Inc.

Pao-Cheng Chiu

Chen-Chih Huang

Kang-Wei Hsueh

Hung-Sung Li

Ya-Lun Yang

Zwei-Mei Lee

Chao-Cheng Lee

Wei-Cheng Tang

Kuan-Hua Chao

Chih-Chien Hung

Hung-Yi Hsieh

Wei-Hsin Tseng

Chih-Wen Huang

Ming-Han Lee

Mu-Jung Chen

Chieh-Min Feng

Juiyuan Tsai

A delta-sigma modulator includes a receiving circuit, a loop filter, a quantizer, a dynamic element matching circuit and a digital to analog converter. The receiving circuit is arranged for receiving a feedback signal and an input signal to generate a summation signal. The loop filter is arranged for receiving the summation signal to generate a filtered summation signal. The quantizer is arranged for generating a digital output signal according to the filtered summation signal. The dynamic element matching circuit is arranged for receiving the digital output signal to generate a shaped digital output signal for shaping element mismatch. The digital to analog converter is arranged for performing a digital to analog converting operation upon a signal derived from the shaped digital output signal to generate the feedback signal to the receiving circuit, wherein clock signals used by the quantizer and the dynamic element matching circuit have different frequencies.

Techniques for improving mismatch shaping of dynamic element matching circuit within delta-sigma modulator

Analog-to-digital-converters (ADC) are provided. The ADC contains a first capacitive digital-to-analog-converter (CDAC) and a control circuit. The CDAC, including n bit, is configured to connect a kth bit of the n bits to a first voltage reference to provide a first analog signal, convert the first analog signal into first digital code using 0th through (k&#x2212;1)th bits that are less significant than the kth bit, connect the kth bit of the n bits to a second voltage reference to provide a second analog signal, and convert the second analog signal into second digital code using the 0th through (k&#x2212;1)th bits that are less significant than the kth bit. The control circuit is configured to estimate a weight of the kth bit based on the first and second digital code.

Calibration and noise reduction of analog to digital converters

A communication circuit and a communication device are provided. The communication circuit includes first, second, and third RF transceivers, first and second baseband transceivers, and first and second modem circuits. The first and second RF transceivers are configured to down-convert first and second RF signals for MIMO. The third RF transceiver is configured to down-convert a third RF signal for a second telecommunication technology. The first baseband transceiver is configured to digitize the down-converted first RF signal to output a first baseband signal. The second baseband transceiver is configured to digitize one of the down-converted second or third RF signals according to a selection signal to output a second baseband signal. The first modem circuit is configured to digitally process the first and second baseband signals using the MIMO technology. The second modem circuit is configured to digitally process the second baseband signal using the second telecommunication technology.

Communication circuits and communication devices supporting MIMO and dual-mode techniques

A voltage controlled oscillator comprising first and second differential delay cells. The first differential delay cell has a first control voltage input terminal. The second differential delay cell is coupled to the first differential delay cell in a loop and has a second control voltage input terminal. The second voltage input terminal is disconnected from the first voltage control input terminal. The first voltage control input terminal receives a first voltage signal, and the second voltage control input terminal receives a second voltage signal different from the first voltage signal.

Voltage controlled oscillators and phase-frequency locked loop circuit using the same

A track and hold amplifier is provided. The track and hold amplifier includes an input node receiving an analog signal, a buffer coupled between a first node and an output node, a first switch coupled between the input node and the first node, a plurality of switching circuits and a voltage generating unit. Each of the switching circuits includes a capacitor coupled between the first node and a second node. The voltage generating unit selectively provides a common signal or a reference signal to the capacitors of the switching circuits, wherein the reference signal is independent from the analog signal.

Track and hold amplifiers and analog to digital converters

The invention provides a serial link transmitter coupled to a serial link receiver through a pair of transmission lines and having a pair of transmitting terminals respectively coupled to one of the transmission lines. The serial link transmitter comprises a differential amplifier and a voltage clamping circuit. The differential amplifier generates a pair of differential output voltages on the transmitting terminals according to a pair of differential input voltages for transmitting data to the serial link receiver, and the differential output voltages are transmitted with a common mode voltage to the serial link receiver during data transmission. The voltage clamping circuit clamps the pair of differential output voltages of the transmitting terminals to the common mode voltage before the serial link transmitter transmits data to the serial link receiver.

Serial link transmitter

A sampling circuit includes an amplifier, a sampling capacitor, a feedback capacitor, and a voltage source. The sampling capacitor and the feedback capacitor are coupled to the same input terminal of the amplifier, such that the offset of the amplifier and low-frequency noise can be cancelled. The voltage source can shift the voltage level of an output signal of the sampling circuit by the difference between the input and output common mode voltages of the amplifier, so that an amplifier having different input common mode voltage and output common mode voltage can be adopted, and the capacitance of the sampling capacitor and that of the feedback capacitor can be different, resulting in a non-unit gain.

Sampling circuits

A low to high voltage conversion output driver. The low to high voltage conversion output driver has an output coupled to a first fixed voltage via a load device and comprises a current source, a low voltage transistor, and a high voltage transistor. The current source has one end coupled to a second fixed voltage. The low voltage transistor has a first terminal coupled to the other end of the current source, a second terminal receiving a low voltage data signal, and a third terminal. The high voltage transistor has a first terminal coupled to the third terminal of the low voltage transistor, a second terminal coupled to a bias source, and a third terminal coupled to the output.

Low to high voltage conversion output driver

A track and hold amplifier is provided. The track and hold amplifier includes an input node receiving an analog signal, a buffer coupled between a first node and an output node, a first switch coupled between the input node and the first node, a plurality of switching circuits and a voltage generating unit. Each of the switching circuits includes a capacitor coupled between the first node and a second node. The voltage generating unit selectively provides a common signal and a reference signal to the capacitors of the switching circuits, wherein the reference signal is independent from the analog signal and the common signal.

A transceiver in a full duplex communication system includes a hybrid circuit for transmitting a transmission signal or receiving a receive signal via the channel, the hybrid circuit includes an echo cancellation device for removing transmission signal components from the receive signal; wherein the hybrid circuit outputs a processed receive signal; and a gain amplifier being an OP-RC AGC is directly connected to the hybrid circuit for amplifying the processed receive signal, wherein a first node of the gain amplifier coupled to the echo cancellation device is a virtual ground.

Transceiver for full duplex communication systems

The invention relates to a phase-interpolation circuit and a phase-interpolation signal generating circuit applying the phase-interpolation circuit. The phase-interpolation circuit can avoid short-circuit current effectively. In addition, an inter-phase signal can be interpolated between the rising edge and the falling edge of the clock pulse. The phase-interpolation signal generating device can generate multiphase clock signals which not only have linearly distributed phases but also maintain good 50% duty cycle of the multiphase clock signals.

Phase interpolation circuit

A switching regulator includes a reference voltage generator and a switching-regulating module. The reference voltage generator receives a digital control signal and generates a reference voltage according to the digital control signal. The switching-regulating module is connected to the reference voltage generator and generates an output voltage according to the reference voltage. The value of the digital control signal is gradually increased to make the reference voltage being gradually increased at the initial stage of the activation of the switching regulator.

Switching regulator

A signal transmitting apparatus being used in a network device includes a voltage-controlled current source for outputting a current signal according to an input digital signal; a line driver for outputting a voltage signal according to the current signal; at least one impedance-matching unit, which is coupled to the line driver, for impedance-matching at the output of the line driver; and a first correction unit, which is coupled to the voltage-controlled current source, for outputting a first correction signal to adjust the current signal outputted from the voltage-controlled current source.

Network transmitting unit with correction function

A multiple-phase switching circuit includes an alternative signal generator for generating a plurality of alternative signals according to a switching signal, and a multiplexer for receiving a plurality of clock signals and outputting a target clock signal according to the alternative signals. Only one of the alternative signals generated by the alternative signal generator is in a first logic level, while the other alternative signals are in a second logic level. The alternative signal generator changes the logic level of a first alternative signal having the first logic level into the second logic level, and changes the logic level of a second alternative signal adjacent to the first alternative signal into the first logic level.

Multiple-phase switching circuit

A high-to-low level shifter, coupled to a first external signal, for transforming the first external signal into an internal signal, wherein the first external signal substantially switches between a high-voltage-domain high potential and a high-voltage-domain low potential, the internal signal substantially switches between a low-voltage-domain high potential and a low-voltage-domain low potential. The high-to-low level shifter includes: an inverter, for generating a second external signal according to the first external signal, wherein the second external signal is inverse to the first external signal; and a level shifter, for generating the internal signal according to the first external signal and the second external signal.

Growing community of inventors

Taipei County, Taiwan

Pao-Cheng Chiu