Intel Corporation

Pannerkumar Rajagopal

Karunakara Kotary

Prakash Pillai

Sagar C Pawar

Ovais F Pir

Raghavendra N

Sriram Ranganathan

Raghavendra Nagaraj

Rajesh Poornachandran

Prashant Dewan

Sean Dardis

Naveen G

Aneesh A Tuljapurkar

Vishwanath Somayaji

Satish Muthiyalu

Mohamed Haniffa

Govindaraj Gettimalli

Mihir Shah

Vinithra Janarthanan

Nagabhushan Reddy

Santhosh Raghuram Krishnaswamy

Radhakrishna Pai

Saravanakumar Ulaganathan

Javahar Ragothaman

Siddharth Selvaraj

Abhinay Gupta

Kiran Mahesh Eriki

Bhavana Shankarappa

Siddhartha Selvaraj

Murali R Iyengar

Sahil Dureja

Methods and apparatus for adaptive keyboard scanning are disclosed. A disclosed example apparatus to adaptively control operation of a keyboard includes at least one memory, instructions, and processor circuitry. The processor circuitry is to determine whether to operate the keyboard in a first mode or in a second mode different from the first mode, the first mode corresponding to a first number of keys, the second mode corresponding to a second number of keys less than the first number of keys, and set the keyboard to operate in the first mode or the second mode based on the determination.

Methods and apparatus for adaptive keyboard scanning

An apparatus comprises a first circuitry to perform, in response to a first message from an operating system, a first process to place a computer device in a first operating mode, store state information in a volatile memory of the computer device, and start a timer for a time-out period for performing the first process. First components of the computer device are in a low power state. A second circuitry to detect, after the time-out period, a failure of the first process. A third circuitry to perform, in response to the detected failure of the first process, a second process to place the computer device in a second operating mode and store state information in a non-volatile memory of the computer device. The volatile memory is operational in the first operating mode and is in a low power state in the second operating mode.

Apparatus and method for achieving deterministic power saving state

The disclosure generally relates method, system and apparatus to prevent denial of service (DOS) attacks on PCIe based computing devices. In an exemplary embodiment, an independent register is used in combination with a filter driver and additional logic to form an integrity check for power down instructions. An exemplary system includes a register circuitry corresponding to the IP device, the register circuitry having a designated storage bit to indicate an unlocked state of the register; a filter driver to receive a first power state transition request when the IP device is idle after a predetermined period, the power state transition request defining a timeout period; a controller to change the power state of the IP device to the unlock state; a decision logic to receive and authenticate a second power state transition request in response to validation of register circuitry being unlocked.

Method, system and apparatus to prevent denial of service attacks on PCIe based computing devices

A Peripheral Component Interface Express (PCIe) card includes a circuit board, a device mounted on the circuit board, and a PCIe processor mounted on the circuit board. The PCIe processor is communicatively coupled to the device and a host processor of a host system. The PCIe processor is configured to detect a power signal on an auxiliary (AUX) power rail of the PCIe card. A periodic detection of a state of the device is performed based on detecting the power signal on the AUX power rail. A signal indicative of the state of the device is encoded for transmission to the host processor of the host system. PCIe link training is performed via a PCIe interface with the host system. The PCIe link training is initiated based on the signal indicative of the state of the device.

PCIe deterministic link training using OOB communications and enumeration optimization during different power-up states

A power-management scheme where when a system-on-chip (SoC) is in an active state, control and monitoring logic or circuitry turns off all wake logic or circuits for various associated intellectual property (IP) blocks. Based on user defined operating system power manager (OSPM) policies, OSPM kicks off an interrupt to the control and monitoring logic or circuitry to turn off or power gate the wake logic for individual IP blocks in the SoC. As such, wake logic that are idle in active state (e.g., S0 state) and would otherwise draw power in the S0 state are now turned off, thus saving power and/or extending battery life for the system. When the SoC is in a low power state, then the control and monitoring logic or circuitry selectively turns on the wake logic for the associated IP blocks based on detected user presence for the computing system having the SoC.

Power management of a processor and a platform in active state and low power state

A scheme for restoring a password-protected endpoint device (e.g., a memory device) of a computer system to an operational state from a low power state without requiring user input of a device password. A password received for unlocking the device during a boot process is stored in a secure memory. The password-protected endpoint device subsequently enters the low power state, causing it to lock. During a transition from the low power state to an operational state, it is detected that the password for the endpoint device is stored in the secure memory. The password is fetched from the secure memory and used to unlock the endpoint device, thereby restoring the endpoint device to an operational state.

Apparatus and method for restoring a password-protected endpoint device to an operational state from a low power state

Systems, apparatuses and methods may provide for technology that enables, during a boot sequence, a first set of ranks in a memory module based on a battery status and a user interface and disables, during the boot sequence, a second set of ranks in the memory module based on the battery status and the user interface. The technology may also generate a map between a system address space and a first set of banks in the first set of ranks and exclude a second set of banks in the first set of ranks from the map.

Configurable reduced memory startup

An apparatus and method are provided which take advantage of heterogeneous compute capability to dynamically pick the best operating core for BIOS power-up flows and sleep exit flows (e.g., S3, S4, and/or S5). The selection of the BSP is moved to an early power-up time instead of a fixed hardware selection at any time. For maximum boot performance, the system selects the fastest capable core as the BSP at an early power-up time. In addition, for maximum power saving, the system selects the most power efficient core as the BSP. Processor or switching for selecting the BSP happens during the boot-up as well as power-up flows (e.g., S3, S4, and/or S5 flows).

Apparatus and method for dynamic selection of an optimal processor core for power-up and/or sleep modes

Described is a system where memory can be allocated for use by an adapter pre-boot and preserved for use post-boot. A BIOS can allocate for pre-boot hardware operations (e.g., graphics drivers, framebuffers, etc.) and mark this allocated memory as preserved. An indication of the allocated memory can be provided for an OS, such that post-boot, the OS can reclaim and reallocate this memory.

Reclaiming and reusing pre-boot reserved memory post-boot

An apparatus to facilitate memory map security in a system on chip (SOC), is disclosed. The apparatus includes a micro controller to receive a request to grant a host device an access to a memory device and perform an alias checking process to verify accuracy of a memory map of the memory device.

Memory map protection mechanism

A Power Management Controller (PMC) which manages power states of a platform, informs a power accumulator device to start measuring the platform power during entry into the low power state (e.g., S0iX). The power accumulator device starts measuring the power until a stop message comes from the PMC. The PMC on detection of any wake event initiates a stop message to the power accumulator device. Once an operating system (OS) context is restored, software can read the measured data from the power accumulator device. The measured data is accessible to a host software using standard software application programming interface (API) and can be used to influence the power policies of the system.

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Bengaluru, India

Pannerkumar Rajagopal