Nxp B.v.

Pankaj Shrivastava

Ata Khan

Greg Goodhue

Craig A MacKenna

Zhimin Ding

Gregory Goodhue

Rick Varney

Prithvi Nagaraj

Bas Van Der Veer

Aspects of the disclosure are directed to a system having a particularly-configured microcontroller. In one embodiment, the microcontroller includes the following: a processor; a processor data bus connected to the processor; a set of peripherals; a peripheral data bus connected to the peripherals; a peripheral bus bridge providing an interface between the processor data bus and the peripheral data base and including a plurality of special function register bank blocks that are internal to the microcontroller, each register bank block having a respective output; and a register bank block decoder circuit for decoding interrupts to provide a selection output for activation of one of the plurality of register bank blocks.

Microcontroller with an interrupt structure having programmable priority levels with each priority level associated with a different register set

A microcontroller () includes a processor (), an embedded memory () operatively coupled to the processor (), and a microcontroller test interface () operatively connected to the processor () and the memory (). The microcontroller () responds to a reset signal to perform a reset initiation that causes an initial disabled state of the test interface () to be set and execution of initiation code with the processor (). This code execution optionally establishes a further disabled state. The microcontroller () provides an enabled state of the test interface for memory () access through the test interlace () during microcontroller () operation subsequent to the reset initiation unless the further disabled memory () access state is established by execution of the initiation code.

Controlling access to an embedded memory of a microcontroller

One embodiment of the present application includes a microcontroller () that has an embedded memory (), a programmable processor (), and a test interface (). The memory () is accessible through the test interface (). In response to resetting this microcontroller (), a counter is started and the test interface () is initially set to a disabled state while an initiation program is executed. The test interface () is changed to an enabled state&#x2014;such that access to the embedded memory () is permitted through it&#x2014;when the counter reaches a predefined value unless the microcontroller () executes programming code before the predefined value is reached to provide the disabled state during subsequent microcontroller () operation.

Embedded memory protection

One embodiment of the present invention is a microcontroller () including an embedded memory (), waveform control circuitry () operatively coupled to the memory (), several terminals (), and a programmable processor (). Processor () is responsive to execution of the first sequence of instructions to store a waveform bit pattern in memory () with a desired transmission timing. Waveform circuitry () is responsive to processor () to control transmission of the waveform bit pattern stored in memory () through one or more of the terminals () in accordance with the timing while processor () executes the second sequence of instructions to perform a different process.

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San Jose, CA, United States of America

Pankaj Shrivastava