Stmicroelectronics S.r.l.

Stmicroelectronics International N.v.

Stmicroelectronics Pvt. Ltd.

Pankaj Rohilla

Abhishek Jain

Andrea Mario Veggetti

Luca Ciccarelli

Claudio Mucci

Valentina Nardone

Massimiliano Innocenti

Matteo Pizzotti

The present disclosure relates to a low consumption flip-flop circuit with data retention, comprising at least one flip-flop and at least one retention cell connected to the output of the flip-flop and configured so that during normal operation of the flip-flop circuit, the retention cell transmits the data or logic state present on the output terminal of the flip-flop to its own output terminal, while during low consumption operation of the flip-flop circuit a latch circuit of the retention cell suitable to memorize data or a logic state corresponding to the last data or logic state present on the output terminal of the flip-flop is activated.

Low consumption flip-flop circuit with data retention and method thereof

A base cell for an Engineering Change Order (ECO) implementation having at least a first pair of CMOS transistors and a second pair of CMOS transistors, characterized in that said at least first pair of CMOS transistors have a common gate and said at least second pair of CMOS transistors have separate gates.

Base cell for engineering change order (ECO) implementation

Growing community of inventors

New Delhi, India

Pankaj Rohilla