International Business Machines Corporation

Cryptography Research, Inc.

Thomson Consumer Electronics Inc.

Pankaj Rohatgi

Paul Carl Kocher

Joshua M Jaffe

Pau-Chen Cheng

Grant W Wagner

Josyula R Rao

Paul Ashley Karger

Angela Marie Schuett

Zhen Liu

Anton Viktorovich Riabov

Michael Steiner

Craig Edward Hampel

Elke De Mulder

Sami James Saab

Shai Halevi

Ronald Perez

Trent Ray Jaeger

Kay Schwendimann Anderson

Helmut Scherzer

Suresh N Chari

Genady Grabarnik

Ramakrishnan Srikant

Vincenzo Valentino DiLuoffo

Nagui Halim

Elaine Rivette Palmer

Mark David Feblowitz

Rosario Gennaro

Ralf Rantzau

Tal D Rabin

Michael Hutter

Bruce Roy Archambeault

David Claude Toll

Winthrop Wu

Christopher Gori

Jeremy Cooper

Claudia Keser

Weifeng Chen

David Carroll Challener

Dakshi Agrawal

Vincent Louis Dureau

Vijay A Kumar

David R Safford

Charanjit Singh Jutla

Dhruv Manmohandas Desai

Michael Alexander Hamburg

Pradeep Kumar Dubey

Matthew Pond Baker

Denis Alexandrovich Pochuev

Alexandre Valentinovich Evfimievski

Joel Patrick Wittenauer

Amit Kapoor

Genady Ya Grabarnik

Rodrigo Portella Do Canto

Atri Rudra

Trenton Ray Jaeger

Marc Lelarge

Angela Schuett Reninger

Alexandre V Evfunievski

John Andrew Clark

Yow Tzu Lim

A method for performing a security chip protocol comprises receiving, by processing hardware of a security chip, a message from a first device as part of performing the security chip protocol. The processing hardware retrieves a secret value from secure storage hardware operatively coupled to the processing hardware. The processing hardware determines a path through a key tree based at least in part on the message. The processing hardware derives a validator at least in part from the secret value using a sequence of entropy redistribution operations associated with the path through the key tree. The processing hardware exchanges the validator between the security chip and the first device as part of the security chip protocol in order to authenticate at least one of the security chip or the first device.

Security chip with resistance to external monitoring attacks

The embodiments described herein describe technologies to address initial establishment of device credentials in an Internet of Things (IoT) infrastructure. The embodiments are directed to unifying secure credential establishment regardless of the endpoint type, thus addressing the challenge of a great diversity among IoT devices. This approach is designed to address a challenge of initial trusted enrollment of the IoT endpoints into a secure infrastructure, which allows secure communications between the devices in the IoT environment.

Internet of things (IoT) device management

Systems and methods for performing cryptographic data processing operations in a manner resistant to external monitoring attacks. An example method may comprise: executing, by a processing device, a first data manipulation instruction, the first data manipulation instruction affecting a state of the processing device; executing a second data manipulation instruction, the second data manipulation instruction interacting with said internal state; and breaking a detectable interaction of the first data manipulation instruction and the second data manipulation instruction by executing a third data manipulation instruction utilizing an unpredictable data item.

Performing cryptographic data processing operations in a manner resistant to external monitoring attacks

Embodiments herein facilitate resisting side channel attacks through various implementations and combinations of implementations. In embodiments, this is accomplished by preventing sensitive data from consecutively following other data through potentially vulnerable resources which otherwise may cause data to leak. Where such vulnerabilities to attacks are known, suspected, or as a proactive precaution, a cleaner can be used to inhibit the sensitive data from passing through the vulnerable areas consecutively and thus inhibit the leakage. Embodiments also envision utilizing certain types of circuits to assist in preventing leakage. By using such circuits one can reduce or even potentially eliminate the requirement for cleaners as mentioned previously.

Enhancements to improve side channel resistance

An indication of a mode of operation to be performed with a block cipher may be received. Logic associated with the block cipher may be configured based on the indicated mode of operation to be performed with the block cipher. Furthermore, an input data and a mask data may be received. The input data may be combined with the mask data to generate a masked input data based on the configured logic. The masked input data may be provided to the block cipher based on the configured logic and an output data may be generated with the block cipher based on the provided masked input data.

Programmable block cipher with masked inputs

Input signals may be received. Furthermore, a control signal controlling the implementation of a Differential Power Analysis (DPA) countermeasure may be received. One of the input signals may be transmitted as an output signal based on the control signal. A cryptographic operation may be performed based on the first output signal that is transmitted based on the control signal.

Configuring a device based on a DPA countermeasure

Share values for use in a cryptographic operation may be received and the cryptographic operation may be performed based on the share values. A pseudorandom number that is to be used by the cryptographic operation may be identified and the pseudorandom number may be generated based on a portion of the share values that are used in the cryptographic operation. The cryptographic operation may then be performed based on the generated pseudorandom number.

Generating a pseudorandom number based on a portion of shares used in a cryptographic operation

A method for device authentication comprises receiving, by processing hardware of a first device, a message from a second device to authenticate the first device. The processing hardware retrieves a secret value from secure storage hardware operatively coupled to the processing hardware. The processing hardware derives a validator from the secret value using a path through a key tree. The first device then sends the validator to the second device.

Apparatus with anticounterfeiting measures

Systems and methods for performing cryptographic data processing operations in a manner resistant to external monitoring attacks. An example method may comprise: executing, by a processing device, a first data manipulation instruction, the first data manipulation instruction affecting an internal state of the processing device; executing a second data manipulation instruction, the second data manipulation instruction interacting with said internal state; and breaking a detectable interaction of the first data manipulation instruction and the second data manipulation instruction by executing a third data manipulation instruction utilizing an unpredictable data item.

A computing device includes a secure storage hardware to store a secret value and processing hardware comprising at least one of a cache or a memory. During a secure boot process the processing hardware loads untrusted data into at least one of the cache or the memory of the processing hardware, the untrusted data comprising an encrypted data segment and a validator, retrieves the secret value from the secure storage hardware, derives an initial key based at least in part on an identifier associated with the encrypted data segment and the secret value, verifies, using the validator, whether the encrypted data segment has been modified, and decrypts the encrypted data segment using a first decryption key derived from the initial key to produce a decrypted data segment responsive to verifying that the encrypted data segment has not been modified.

Secure processor with resistance to external monitoring attacks

A method for device authentication comprises receiving, by processing hardware of a first device, a message from a second device to authenticate the first device. The processing hardware retrieves a secret value from secure storage hardware operatively coupled to the processing hardware. The processing hardware derives a validator from the secret value using a path through a key tree, wherein the path is based on the message, wherein deriving the validator using the path through the key tree comprises computing a plurality of successive intermediate keys starting with a value based on the secret value and leading to the validator, wherein each successive intermediate key is derived based on at least a portion of the message and a prior key. The first device then sends the validator to the second device.

System and method for secure authentication

Growing community of inventors

Los Altos, CA, United States of America

Pankaj Rohatgi