Apple Inc.

Pankaj Lnu

Shingo Suzuki

Mridul Agarwal

Pradeep Kanapathipillai

Gideon N Levinsky

Richard F Russo

Kulin N Kothari

Nikhil Gupta

Rajat Goel

Matthew R Johnson

Raghava Rao V Denduluri

Edvin Catovic

An apparatus includes a cache memory circuit, and a hierarchal store queue circuit that further includes a primary queue and a secondary queue. The hierarchal store queue circuit may be configured to write incoming store requests to the primary queue in response to the primary queue currently having capacity, and to write incoming store requests to the secondary queue in response to the primary queue currently not having capacity. The hierarchal store queue circuit may be further configured to commit store requests to the cache memory circuit from the primary queue but not from the secondary queue. In response to a determination that the primary queue currently has capacity, the hierarchal store queue circuit may perform a transfer of at least one store request from the secondary queue to the primary queue.

Hierarchical store queue circuit

A processor includes an instruction issue circuit, and high-utilization and low-utilization execution unit circuits coupled to execute instructions received from the instruction issue unit. On average, utilization of the low-utilization execution unit circuit is lower than utilization of the high-utilization execution unit circuit. The processor also includes a retention circuit coupled to a different power domain than the low-utilization execution unit circuit, and a power management circuit. The power management circuit may be configured to detect that inactivity of the low-utilization execution unit circuit satisfies a threshold inactivity level; upon detecting that the threshold inactivity level is satisfied, cause architecturally-visible state of the low-utilization execution unit circuit to be copied to the retention circuit; and subsequent to copying of the architecturally-visible state to the retention circuit, cause the low-utilization execution unit circuit to enter a power-off state, where the retention circuit retains stored data during the power-off state.

Execution unit power management

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Pankaj Lnu