Intel Corporation

Sk Hynix Nand Product Solutions Corp.

Pankaj Kumar

Hang T Nguyen

Christopher Houghton

David A Biermann

Mark A Schmisseur

Sivakumar Radhakrishnan

Samantha J Edirisooriya

Sin Sim Tan

Geetani R Edirisooriya

Kenneth C Haren

Blaine Monson

Michael T Klinglesmith

Bradley A Burres

Eric Dahlen

Thomas M Slaight

Brian M Leitner

Marc Tim Jones

David C Lee

Matthew R Wilcox

Roger C Jeppsen

Saptarshi Mondal

Vinodh Gopal

Wajdi K Feghali

Mark A Yarch

Shanker R Nagesh

Thomas C Brown

K L Siva Prasad Gadey N V

Steven C Miller

John Alan Miller

Marc A Goldschmidt

Timothy J Jehl

Peter Molnar

In accordance with embodiments disclosed herein, there are provided methods, systems, mechanisms, techniques, and apparatuses for presentation of direct accessed storage under a logical drive model; for implementing a distributed architecture for cooperative NVM Data protection; data mirroring for consistent SSD latency; for boosting a controller's performance and RAS with DIF support via concurrent RAID processing; for implementing arbitration and resource schemes of a doorbell mechanism, including doorbell arbitration for fairness and prevention of attack congestion; and for implementing multiple interrupt generation using a messaging unit and NTB in a controller through use of an interrupt coalescing scheme.

Presentation of direct accessed storage under a logical drive model

A compute device for operation in a rack of a data center includes a substrate, a solid state drive array, a fan array, and a plurality of physical resources. The components of the compute device are arranged on the substrate to prevent or reduce shadowing of heat-producing physical resources, such as a processor, by other heat-producing physical resources relative to an airflow generated by the fan array. To do so, ruler solid state drives are used to facilitate positioning of the fan array toward a front edge of the substrate.

Technologies for improving processor thermal design power

A processing system includes a processor and a VM-to-VM communication accelerator circuit comprising a first interface device to support direct memory access (DMA) data transfers by the first VM, a register to store a reference to a primary physical function (PF) associated with the first interface device, wherein the first primary PF is associated with an access control table (ACT) specifying an access permission for the first VM with respect to a second VM, and a direct memory access (DMA) descriptor processing circuit to process, using a working queue associated with the first primary PF, a DMA descriptor referencing a request for a DMA data transfer between the first VM and the second VM, and execute, using the first interface device, the DMA data transfer based on the access permission.

Hardware-based virtual machine communication supporting direct memory access data transfer

In one embodiment, an apparatus comprises a processor core and a power control unit. The power control unit is to identify the occurrence of a power loss from a primary power source, instruct the I/O controller to block further write requests from the one or more I/O devices and to send at least one pending write request stored by the I/O controller to the memory controller, and instruct the memory controller to complete at least one pending write request stored by the memory controller and to cause the memory to be placed into a self-refresh mode.

Method and apparatus for completing pending write requests to volatile memory prior to transitioning to self-refresh mode

In one embodiment, the present invention includes a processor having a plurality of cores and a control logic to control provision of a voltage/frequency to a first core of the plurality of cores independently of provision of a voltage/frequency to at least a second core of the plurality of cores. In some embodiments, the voltages may be provided from one or more internal voltage regulators of the processor. Other embodiments are described and claimed.

Providing per core voltage and frequency control

Hardware-based virtual machine communication

Method, apparatus, and system of detecting a hot-plug event. The hot-plug event detection may be done in-band or out-of-band. The in-band detection is performed by a state machine and the out-of-band detection is performed by a logic. A circuitry is to detect a hot-plug event when inserting or removing a device from an extension bus of the plurality of extension bus slots. The circuit is to generate a hot-plug message to notify the hot-plug event. The circuitry including the state machine, the logic and a register to provide at least two bits to mask at least two states of the state machine.

Method, apparatus, and system for plugin mechanism of computer extension bus

Growing community of inventors

Chandler, AZ, United States of America

Pankaj Kumar