Lsi Corporation

Cisco Technology, Inc.

Advanced Micro Devices Corporation

Hewlett Packard Enterprise Development LP

Juniper Networks, Inc.

Avago Technologies General IP (singapore) Pte. Ltd.

Appdynamics, Inc.

Pankaj Kumar

Pramod Elamannu Parameswaran

Makeshwar Kothandaraman

Vani Deshpande

John Christopher Kriz

Dipankar Bhattacharya

Sanjay Nagaraj

Anuroop Iyengar

Michael Margulis

Jeffrey Jay Nagy

Amod Gupta

Naveen Chandra Srivastava

Janardhan Achanta

Shreekanth Karandoor Sampigethaya

Yehuda Smooha

Xin Zhang

Prabhu Raj V K

David Roth

Karthik Bhat

Paul K Hartley

Magesh Babu Nagalingam

Ashish V Shukla

Jitesh Mulchandani

Kalpeshkumar Girishchandra Dave

Ting Liang

Aswinraj Govindaraj

Vaibhav Anand Srivastava

The disclosed computer-implemented method relating to read-only memory can include (i) asserting a column select signal to select a particular column within a column mux read-only memory, (ii) forwarding, in response to asserting the column select signal, a bit value stored at that particular column to a gate of a transistor that connects a first stage local bitline to a second stage local bitline, and (iii) forwarding an inversion of the bit value to the second stage local bitline through the drain of the transistor for local bitline sensing. Various other methods, systems, and computer-readable media are also disclosed.

Systems and methods for a compressed bitcell read-only memory

A provider edge (PE) device may receive traffic associated with one or more services, wherein the traffic includes a plurality of packets, and may determine, based on the plurality of packets, one or more packets respectively associated with each service of the one or more services. The PE device may determine, based on the one or more packets respectively associated with each service of the one or more services, a respective status of each of the one or more services. The PE device may generate type-length-value (TLV) data that indicates the respective status of each of the one or more services and may cause the TLV data to be added to a link layer discovery protocol (LLDP) packet. The PE device may send the LLDP packet that includes the added TLV data to a customer edge (CE) device.

Service status notification

Examples described herein relate to a system consistent with the disclosure. For instance, the system may comprise a data lake including information relating to an in-store activity of a customer and an online activity of the customer, a processing resource, and a non-transitory machine-readable medium storing instructions executable by the processing resource to identify the in-store activity and the online activity of the customer, aggregate and store the in-store activity and the online activity of the customer in the data lake, reduce an amount of products in a product portfolio, compare purchases including in-store purchases and online purchases, and recommend a product of the plurality of products based on the comparison.

Method and medium for customer product recommendations

A system implements code trampolining techniques by generating custom trampoline functions, compiling the functions, and executing the compiled functions directly from a library when the corresponding native function is called. The native functions may be binary functions, such as functions in C++ code, or other languages. A code generator may read a set of functions to be implemented and generate code, such as binary code, for the destination function. In doing so, the code generator may generate code which matches the source function signature. The generated code may then be compiled into a shared library which is loaded by the process being instrumented. When the library is initiated upon subsequent calls for the native function, the trampoline mechanisms will be set up between the source function and the generated destination function to operate seamlessly with matching signatures.

Dynamic configuration of native functions to intercept

Systems, apparatuses, and methods for reducing the load on the bitlines of a ROM bitcell array are described. The connections between nets of a ROM bitcell array may be assigned based on their programmed values using a traditional approach. Then, a plurality of optimizations may be performed on the assignment of nets to reduce the load on the bitlines of the array. A first optimization may swap the connections between ground and bitline for the nets of a given column responsive to detecting that the number of connections to the corresponding bitline is greater than the number of connections to ground for the given column. A second optimization may remove the connection of a net to a bitline if three consecutive nets of a given column are connected to the bitline.

Reducing the load on the bitlines of a ROM bitcell array

A dynamic monitoring process begins with configuring a start and end method to be monitored. The dynamic monitoring process may intercept both the start and end methods as and when the loader is initiated or at runtime to dynamically attach and detach the instrumentation. A loader may then be modified to call a library method upon detection of the start method. The library method may serve as a notification to the start of the method and causes a reflector to retrieve information from the incoming request. The incoming information may include data from which a business transaction name may be determined. The business transaction name is then associated with the monitoring of the particular request. When an exit call is detected, a call may be made to the library for a method which invokes a decorator. The decorator may insert business transaction name and other data into the outgoing call.

Monitoring and correlating a binary process in a distributed business transaction

Methods and systems for determining latency in a communication network may be provided. A plurality of commands may be sent in the communication network. A response may be received for each of the plurality of commands from the communication network. A pipeline round trip time may be calculated for each of the plurality of commands based on a time of the response for each of the plurality of commands. A total round trip time for the plurality of commands may be calculated based on the calculated pipeline round trip time. A time saving may be calculated for at least one of the plurality of commands serviced locally.

Algorithm for latency saving calculation in a piped message protocol on proxy caching engine

Systems, apparatuses, and methods for reducing the area of a semiconductor structure. A spacing violation may be detected for a gap width used to separate first and second regions of a layer of semiconductor material. In response to detecting the violation, the first and second regions are merged into a combined region, and then a cut mask layer is formed above the combined region. Next, an etch process is performed through the cut mask layer to remove an exposed third region within the combined region, wherein the exposed third region is interposed between first and second region portions of the combined region.

Using a cut mask to form spaces representing spacing violations in a semiconductor structure

An apparatus comprising a first stage and a second stage. The first stage may be configured to generate an intermediate signal having a first voltage in response to an input signal having a second voltage received from a pad. The second stage may be configured to generate a core voltage in response to the first voltage. The voltage received from the pad may operate at a voltage compliant with one or more published interface specifications.

Low power receiver for implementing a high voltage interface implemented with low voltage devices

An apparatus comprising a level shifter circuit and a control circuit. The level shifter circuit may be configured to generate a differential output in response to (i) a first differential input, (ii) a second differential input and (iii) a first supply. The level shifter circuit comprises a first pull down transistor pair operating with the first supply. The control circuit may be configured to generate the second differential input in response to (i) the first differential input and (ii) a second supply. The control circuit generally comprises a second pull down transistor pair operating with the second supply. The first supply has a higher voltage than the second supply.

Jitter reduction in high speed low core voltage level shifter

A comparison circuit for detecting impedance mismatch between pull-up and pull-down devices in a circuit to be monitored includes a comparator operative to receive first and second signals and to generate, as an output, a third signal indicative of a difference between the first and second signals. A first signal generator is operative to generate the first signal indicative of a difference between reference pull-up and pull-down currents that is scaled by a prescribed amount. The reference pull-up current is indicative of a current flowing through at least one corresponding pull-up transistor device in the circuit to be monitored. The pull-down reference current is indicative of a current flowing through at least one corresponding pull-down transistor device in the circuit to be monitored. A second signal generator connected with the second input of the comparator is operative to generate the second signal as a reference voltage defining a prescribed impedance mismatch threshold associated with the circuit to be monitored.

Impedance mismatch detection circuit

A reference circuit includes an NMOS transistor, a PMOS transistor and a bias circuit. The NMOS transistor includes a source connected with a first voltage supply and a gate adapted to receive a first bias signal. The PMOS transistor includes a source connected with a second voltage supply, a gate adapted to receive a second bias signal, and a drain connected with a drain of the NMOS transistor at an output of the reference circuit. The bias circuit generates the first and second bias signals. Magnitudes the first and second bias signals are configured to control a reference signal generated by the reference circuit such that when the reference signal is near a quiescent value of the reference signal, a current in the reference circuit is below a first level, and when the reference signal is outside of the prescribed limits, the current in the reference circuit increases nonlinearly.

High-voltage tolerant biasing arrangement using low-voltage devices

A compensation circuit for controlling a variation in output impedance of at least one buffer circuit includes a monitor circuit and a control circuit coupled with the monitor circuit. The monitor circuit includes a pull-up portion including at least one PMOS transistor and a pull-down portion comprising at least one NMOS transistor. The monitor circuit is configured to track an operation of an output stage of the buffer circuit and is operative to generate at least a first control signal indicative of a status of at least one characteristic of corresponding pull-up and pull-down portions in the output stage of the buffer circuit over variations in PVT conditions to which the buffer circuit may be subjected. The control circuit is operative to generate a set of digital control bits as a function of the first control signal. The set of digital control bits is operative to compensate the pull-up and pull-down portions in the output stage of the buffer circuit over prescribed variations in PVT conditions.

Hybrid impedance compensation in a buffer circuit

An apparatus comprising a first circuit, a second circuit, and a third circuit. The first circuit may be configured to generate a first control voltage and a second control voltage. The second circuit may be configured to generate a bias signal in response to the first control voltage and the second control voltage. The third circuit may be configured to generate a filtered signal in response to the bias signal. The filtered signal may be added to the first control voltage and the second control voltage to provide AC noise suppression when generating the bias signal.

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Bengaluru, India

Pankaj Kumar