Nvidia Corporation

Pankaj Chaurasia

Shankar Moni

A video processor is described, which is useful for implementing a forward transform process, in compliance with the H.264 standard. The video processor includes an input, for receiving a block of image data. The image data is loaded into an internal register. In response to receiving a SIMD instruction, a multiplier, which incorporates the H.264 forward transform matrix in its associated hardware, processes the block of image data, and writes the resulting partially transformed pixel data back to the internal register, transposing the data during the process.

Forward and inverse transformation of data for video compression

A video processor is described, which is useful for implementing a Hadamard transform process, in compliance with the H.264 standard. The video processor includes an input, for receiving a block of image data. The image data is loaded into an internal register. In response to receiving a SIMD instruction, a multiplier, which incorporates the H.264 Hadamard transform matrix in its associated hardware, processes the block of image data, and writes the resulting partially transformed pixel data back to the internal register, transposing the data during the process.

Hadamard transformation of data for video compression

A video processor is described, which is useful for implementing a quantization process, in compliance with the H.264 standard. The video processor includes an input, for receiving a block of image data. The image data is loaded into an internal register. In response to receiving a SIMD instruction, a quantizer, which incorporates the quantization lookup tables associated with the H.264 standard in its associated hardware, makes necessary high-level quantization decisions. In response to receiving another SIMD instruction, the quantizer uses those high-level quantization decisions to retrieve specific values from the quantization lookup tables.

Forward and inverse quantization of data for video compression

Several different approaches to performing the modulus operation are presented. In one, a method of performing the modulus operation upon a dividend and a divisor within a limited range is discussed. The method involves storing a reference value, receiving a dividend value, and calculating a number of derived inputs. Each of the derived inputs corresponds to the dividend value minus the reference value, and is then further modified by a multiple of the divisor. Using the divisor to select between these derived inputs provides the answer.

Single-cycle modulus operation

A bitstream generator is described, for placing variable length coding (VLC) data into a fixed width data stream. The bitstream generator includes an input for receiving VLC data; the VLC data may be separated into a value component, and a length component. The bitstream generator also includes an output buffer, a memory module, for storing the VLC data before sending. The bitstream generator also incorporates a backup buffer, which is used to store any overflow data which does not fit in the output buffer. A comparator is used, to determine how much of the VLC data will fit in the output buffer. Any portion of the VLC data which does not fit in the output buffer is stored in the backup buffer.

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Sunnyvale, CA, United States of America

Pankaj Chaurasia