US Government as Represented by the Secretary of the Army

USA as Represented by Secretary of the Navy

Pankaj B Shah

H Alfred Hung

Daniel Jonathan Ewing

Michael Andrew Derenge

Vladimir V Mitin

Walter R Buchwald

Tsvetanka Zheleva

A method of substantially offsetting polarization charges in an electronic device having a heterobarrier comprising providing a substrate; providing at least one pair of stacks of semiconductor materials; one of the pair of stacks having one or more of spontaneous and piezoelectric polarity where the total polarization charge is opposite to the other of the pair of stacks; whereby due to the opposing polarities, the polarization is balanced and the pair of stacks operate to store electrical energy.

Semiconductor heterobarrier electron device and method of making

Embodiments of the present invention are directed to semiconductor electronic devices formed of 2-D van der Waals material whose free charge carrier concentration is determined by adjacent semiconductor's polarization. According to one particular embodiment, a semiconductor electronic device is composed of one or more layers of two dimensional (2-D) van der Waals (VDW) material; and one or more layers of polarized semiconductor material adjacent to the one or more layer of 2-D VDW material. The polarization of the adjacent semiconductor material establishes the free carrier charge concentration of the 2-D VDW material.

Semiconductor electronic device formed of 2-D van der Waals material whose free charge carrier concentration is determined by adjacent semiconductor's polarization

An electronic device comprising a substrate; a pair of stacks of polar semiconductor materials which create a charge by spontaneous and/or piezoelectric polarization; one of the pair of stacks having a spontaneous and/or piezoelectric polarity which is in a direction opposite to the other of the pair of stacks; whereby due to the opposing polarities, the polarization is balanced. A method of substantially eliminating the bias required to offset polarization charges in an electronic device having a heterobarrier comprising providing a substrate; growing at least one pair of stacks of semiconductor materials; one of the pair of stacks having a spontaneous and/or piezoelectric polarity which is opposite to the other of the pair of stacks; whereby due to the opposing polarities, the polarization is balanced to substantially eliminate the need for a voltage bias.

A varactor comprising two Schottky diodes, each diode comprising a substrate and a plurality of layers formed on the substrate including at least one GaN layer and at least one semi-insulating material layer formed of a material with an energy gap greater than 3.5 and free carrier mobility less than 300 cm/V-s; the Schottky diodes having cathodes adapted to be connected to an AC voltage input and being configured so that as the AC voltage applied to the cathodes increases the capacitance decreases nonlinearly, the nonlinear transition from high capacitance to low capacitance being adjustable by utilizing the intrinsic carrier concentration of the semi-insulating layer to obtain an optimal nonlinear transition for the predetermined AC voltage applied to the cathodes. A method of making a varactor comprising computer modeling to produce capacitance-voltage curves, modifying at least one semi-insulating region, and modeling power input/output efficiency for a predetermined input signal.

Group III nitride semiconductor frequency multiplier

A preferred method of optimizing a Ga-nitride device material structure for a frequency multiplication device comprises:

Method of optimizing a GA&#x2014;nitride device material structure for a frequency multiplication device

A low-defect gallium nitride structure including a first gallium nitride layer comprising a plurality of gallium nitride columns etched into the first gallium nitride layer and a first dislocation density; and a second gallium nitride layer that extends over the gallium nitride columns and comprises a second dislocation density, wherein the second dislocation density may be lower than the first dislocation density. In addition, a method for fabricating a gallium nitride semiconductor layer that includes masking an underlying gallium nitride layer with a mask that comprises an array of columns and growing the underlying gallium nitride layer through the columns and onto said mask using metal-organic chemical vapor deposition pendeo-epitaxy to thereby form a pendeo-epitaxial gallium nitride layer coalesced on said mask to form a continuous pendeo-epitaxial monocrystalline gallium nitride semiconductor layer.

Low-defect density gallium nitride semiconductor structures and fabrication methods

A structure and method for a silicon carbide (SiC) gate turn-off (GTO) thyristor device operable to provide an increased turn-off gain comprises a cathode region, a drift region having an upper portion and a lower portion, wherein the drift region overlies the cathode region, a gate region overlying the drift region, an anode region overlying the gate, and at least one ohmic contact positioned on each of the gate region, anode region, and cathode region, wherein the upper portion of the drift region, the gate region, and the anode region have a free carrier lifetime and mobility lower than a comparable SiC GTO thyristor for providing the device with an increased turn-off gain, wherein the free carrier lifetime is approximately 10 nanoseconds. The reduced free carrier lifetime and mobility are affected by altering the growth conditions, such as temperature under which epitaxy occurs.

Processing technique to improve the turn-off gain of a silicon carbide gate turn-off thyristor

A technique of spreading current flowing in a semiconductor device comprising an electrode, a drift region adjacent to the electrode, a junction termination extension implant region in the drift region, and a current spreader adjacent to the junction termination extension implant region and the electrode. The current spreader is adapted to reduce current densities and electrostatic fields (preferably simultaneously) in an area connecting the electrode with the drift region. Moreover, the current spreader is adapted to spread current flowing from the electrode into the drift region. The semiconductor device further comprises an ohmic metal contact connected to the electrode and an implant pocket in the drift region, wherein the implant pocket is adapted for terminating electrostatic field lines in the semiconductor device. Preferably, the current spreader comprises an ohmic metal and the electrode comprises any of an anode and a cathode.

Interacting current spreader and junction extender to increase the voltage blocked in the off state of a high power semiconductor device

A method of producing a field emission device includes laying a group III-nitride semiconductor layer over a substrate, placing a photoresist mask over the group III-nitride semiconductor layer, patterning a generally circular grid in the photoresist mask and the group III-nitride semiconductor layer, and forming the group III-nitride semiconductor layer into generally pointed tips using an inductively coupled plasma dry etching process, wherein the group III-nitride semiconductor layer comprises a group III-nitride semiconductor material having a low positive electron affinity or a even a negative electron affinity, wherein the inductively coupled plasma dry etching process selectively creates an anisotropic deep etch in the group III-nitride semiconductor layer, and wherein the inductively coupled plasma dry etching process creates an isotropic etch in the group III-nitride semiconductor layer. Preferably, the photoresist layer is approximately 1.7 microns in thickness, and the fabricated tips have a radius of curvature of less than 100 nanometers.

Method of fabricating sub-100 nanometer field emitter tips comprising group III-nitride semiconductors

Processing technique to improve the turn-off gain of a silicon carbide gate turn-off thyristor and an article of manufacture

A structure and method for a voltage blocking device comprises a cathode region, a drift region positioned on the cathode region, a gate region positioned on the drift region, an anode region positioned on the gate region and a plurality of contacts positioned on each of the cathode region, the gate region, and the anode region, wherein the drift region comprises multiple epilayers having first doped type layers surrounding second doped type layers, wherein dopant concentrations of the first doped type layers are lower than dopant concentrations of the second doped type layers. The epilayers comprise at least one i-n-i layer and/or at least one i-p-i layer. Moreover, the multiple epilayers are operable to block voltages in the device.

Silicon carbide power devices having increased voltage blocking capabilities

A SiC gate turn-off (GTO) thyristor that exhibits improved greatly performance includes a p-type anode region, a n-type gated base region positioned beneath the anode region, a n-type drift region positioned beneath the gated base region and doped to a lower concentration of donors than that of the gated base region, a p-type buffer region positioned beneath the n-type drift region and doped with acceptors to a concentration whose magnitude lies between the doping concentration of the anode region and the drift region, and an n-type substrate positioned beneath the buffer region. In another aspect of the invention of this application, a silicon or silicon carbide gate-turn-off thyristor includes a GTO thyristor structure with a thick buffer layer having a high, free-carrier recombination rate.

Silicon carbide (SiC) gate turn-off (GTO) thyristor structure for higher turn-off gain and larger voltage blocking when in the off-state

A gate turn-off thyristor includes a substrate formed of n-type silicon carbide; a growth buffer formed of n-type silicon carbide and positioned to overlie said substrate; a field buffer region formed of p-type silicon carbide and positioned to overlie said growth buffer; a drift region formed of p-type silicon carbide and positioned to overlie said field buffer region; a gated base region formed of n-type silicon carbide and positioned to overlie said drift region; a modified anode region formed of first, second and third layers of silicon carbide and positioned to overlie said gated base region, said first layer comprising p-type silicon carbide and disposed adjacent said gated base region, said second layer comprising n-type silicon carbide and disposed adjacent said first layer, said third layer comprising p-type silicon carbide and disposed adjacent said second layer; an anode contact disposed on said third layer of said modified anode region; a cathode contact disposed on said substrate; and a gate contact disposed on said gated base region.

Modified-anode gate turn-off thyristor

A Silicon Carbide (SiC) Gate Turn-Off (GTO) thyristor is formed of a substrate having at least three epi-layers provided thereon as first, second and third doped regions, respectively, and the substrate being a fourth doped region, wherein the at least four doped regions alternate between a p-type doping and an n-type doping, with the regions being at least partially overlaid. An anode is arranged on the first region, and a base is arranged on the second region. A controlling gate is arranged on the third region, and a cathode is arranged on the fourth region. A current divider divides the load current between the anode and the base. This reduces the voltage drop of a portion of the load current passing through the thyristor, allowing for the switching of higher current densities than in prior art thyristors, faster switching speeds and reduced junction temperatures.

Silicon carbide (SIC) gate turn-off (GTO) thyristor apparatus and method for high power control

A high speed, compact and reliable semiconductor device for spatially switching light in optical switching networks, optical computers and optical interconnection networks is provided. The semiconductor device for spatially switching light comprises stacked P-anode, inner n-base, inner p-base and cathode layers, with an anode cathode on the P-anode layer defining a ridge. A low reverse bias is provided by a biasing means connected to a gate electrode disposed on a ledge of one base layer. A light emission region on the gate electrode side emits light, and a current flow induces a transversely flowing, narrow, light emitting channel that can be spatially shifted by switching the single gate electrode's bias. A high reverse bias also provides a spatially shifted light emission region in another part of the device's face. A cathode electrode is disposed on a portion of the bottom surface of the N-cathode layer, below the gate electrode and most of the cathode region below the ridge is not covered by the cathode electrode. Other embodiments include related variations, a semiconductor device for spatially switching light in a laser and a semiconductor device for spatially switching light in a selective amplifier for optical switching networks, optical computers, optical interconnection systems and related uses. The location of the cathode electrode is important because it induces the horizontal current flow in the cathode region, that is required for the existence of the transversely flowing, narrow, light emitting channel.

Growing community of inventors

Rockville, MD, United States of America

Pankaj B Shah