Nxp B.v.

General Electric Company

Pankaj Agrawal

Sushil Kumar Gupta

Janakiraman Narayanan

Mahesh Jaywant Rane

Ashish Panpalia

Yatin Vilas Newase

Soundararajan Narayanasamy

Ramesh G Karpur

Simhadri Ramalingeswara Rao Gupta

Jitendra Prabhakar Harshey

Ronak Prakashchandra Trivedi

A low dropout regulator includes a proportional-to-absolute-temperature (PTAT) circuit, an amplification circuit, and an output circuit. The PTAT circuit outputs one current, and the amplification circuit outputs one or more currents. The one or more currents are outputted by the amplification circuit based on collector-emitter voltages associated with transistors of the PTAT circuit. Alternatively, the one or more currents are outputted by the amplification circuit based on the current outputted by the PTAT circuit and the collector-emitter voltages associated with the transistors of the PTAT circuit. The output circuit generates one or more output voltages based on at least one of a base-emitter voltage associated with a transistor of the PTAT circuit and a current of the one or more currents outputted by the amplification circuit.

Low dropout regulator

A pipeline analog-to-digital converter (ADC) includes a hybrid multiplying digital-to-analog converter (MDAC) that includes multiple digital-to-analog converters (DACs), at least one conversion circuit, and at least one amplifier such that a number of conversion circuits and a number of amplifiers is less than a number of DACs. Each DAC is configured to receive an analog input signal in non-overlapping durations of a clock signal and generate a corresponding analog output signal. At least one of the conversion circuits is coupled with at least two DACs, and each conversion circuit is configured to perform conversion operation on a corresponding analog output signal to generate digital signals. At least one of the amplifiers is coupled with at least two DACs, and each amplifier is configured to perform amplification operation on a corresponding analog output signal.

Hybrid pipeline analog-to-digital converter

A sub-ranging analog-to-digital converter (ADC) includes a coarse ADC and a fine ADC that receives a set of coarse signals from the coarse ADC. The fine ADC includes multiple digital-to-analog converters (DACs) and multiple converters such that a number of converters is less than a number of DACs. The DACs and the converters function in a partial time-interleaved manner where each DAC receives an analog input signal in different non-overlapping durations of a clock signal and generates a corresponding analog output signal. At least one of the converters is coupled with at least two DACs, and each converter is configured to receive the corresponding analog output signals and perform conversion operation to generate digital signals in non-overlapping durations of the clock signal, respectively. The durations for performing conversion operation of at least two of the converters overlap partially.

Time-interleaved sub-ranging analog-to-digital converter

A pipeline analog-to-digital converter (ADC) includes a hybrid multiplying digital-to-analog converter (MDAC) that includes multiple digital-to-analog converters (DACs), an amplifier, and a conversion circuit. The multiple DACs function in a pipelined manner such that each DAC receives an analog input signal in different cycles of a clock signal and generates a corresponding analog output signal. The amplifier amplifies each analog output signal to generate a corresponding amplified analog signal in different cycles of the clock signal. The conversion circuit successively approximates each analog output signal to generate multiple digital signals. Thus, a digital output signal of the pipeline ADC is generated based on the corresponding amplified analog signal and at least one of the multiple digital signals. The pipeline ADC utilizes one cycle for performing each of sampling, conversion, and amplification operations, which results into low power consumption by the pipeline ADC.

Pipeline analog-to-digital converter

A sub-ranging analog-to-digital converter (ADC) converts an analog input signal to a digital output signal. The sub-ranging ADC includes a coarse ADC, a fine ADC, and an error correction circuit (ECC). The fine ADC includes at least three digital-to-analog converters (DACs) that are connected in a pipeline architecture. The coarse and fine ADCs receive the analog input signal in a first half cycle of a clock signal. The coarse ADC converts the analog input signal to a first digital signal in a second half cycle of the clock signal. At least one of the first through third DACs converts the analog input signal to a second digital signal in a full cycle of the clock signal. The ECC receives the first and second digital signals and generates the digital output signal.

Sub-ranging analog-to-digital converter

A buck converter is described having a buck converter output for outputting an output supply voltage; a first power supply domain operably coupled to a power source; a second power supply domain; a power supply controller coupled to the first power supply domain, the second power supply domain and the buck converter output; wherein the power supply controller is configured to supply power to the second power supply domain from the first power supply domain or the buck converter output, in dependence of the buck converter output supply voltage. Changing the current supplied to the second power supply domain to the buck converter output may reduce the quiescent current consumption from a battery power source, prolonging battery life.

Buck converter

A contact arm assembly including a plurality of substantially parallel plates having a space between each of the plurality of substantially parallel plates and a plurality of finger assemblies, at least one of the plurality of finger assemblies being pivotally attached to the plurality of substantially parallel plates and being located in the space between each of the plurality of substantially parallel plates, each of the plurality of finger assemblies having a body and an arc runner, the arc runner being locked against the body in at least two locations.

Contact assembly of circuit breaker

An arc chute assembly includes a housing having a lateral axis and a quenching portion disposed within the housing. The quenching portion includes at least two deion plates being spaced along the lateral axis of the housing and each having a cut portion wherein the cut portions are staggered along the lateral axis with respect to one another and are configured to mitigate an arc.

Arc chute assembly for a circuit breaker

A circuit breaker apparatus is provided and includes a circuit breaker, having a housing surface perpendicular to a plane of a front side of the circuit breaker and internal components, a terminal block structurally coupled to the housing surface, first terminal housings arrayed on the terminal block to each support first components and to be receptive of second terminal housings each of which supports second components, at least some of which are electrically coupled to the internal components, to be electrically coupled to at least some of the first components, and an access block. The access block is disposed on the terminal block and has apertures defined therein to provide for front-side access to the first terminal housings.

Growing community of inventors

Bengaluru, India

Pankaj Agrawal