Nxp B.v.

International Business Machines Corporation

Globalfoundries Inc.

Pankaj Agarwal

Jwalant Kumar Mishra

Patrick Van De Steeg

Krishnan Santhana Rengarajan

Rajat Kohli

Shiju K Kandiyil

Jainendra Singh

Vaibhav V Prabhu

A read-only memory (ROM) device includes memory cells, bit-line pairs, a virtual ground line, and a programmable metal track. The memory cells are arranged in an array of rows and columns. Each memory cell stores two bits of data. The virtual ground line is disposed vertically and shared by two adjacent columns. The programmable metal track connects a memory cell to the virtual ground line based on a value of the two bits of data stored in the memory cell.

Dual-bit ROM cell with virtual ground line and programmable metal track

Disclosed is a ROM memory including a first bitcell including a transistor to store two bits and first and second bit lines to read data stored in the bitcell, a second bitcell including a second transistor connected to the first transistor and sharing the first and second bit lines, and a virtual ground line adjacent the bit lines configured to ground the bitcells.

High density ROM cell with dual bit storage for high speed and low voltage

An apparatus includes a memory circuit and a word-line driver circuit. The memory circuit includes a plurality of rows of memory cells, each memory cell in a corresponding row having pass transistors connected to a shared word-line. The word-line driver circuit is configured and arranged to enable pass transistors of a first set of memory cells of the memory circuit by applying a first voltage to word-lines of the first set of memory cells, disable pass transistors of a second set of memory cells of the memory circuit by applying a second voltage to word-lines of the second set of memory cells, and mitigate leakage of pass transistors of a third set of memory cells of the memory circuit by applying a third voltage to word-lines of the third set of memory cells, wherein the third voltage is between the first and second voltages.

Mitigating leakage in memory circuits

A low power sense amplifier for an SRAM is described. A first pass gate transistor is driven by bit line true and a second pass gate transistor is driven by bit line complement. A first pull down transistor driven by the bit line complement is coupled to the first pass gate transistor, and a second pull down transistor driven by the bit line true is coupled to the second pass gate transistor. A data line true is coupled to a node coupling the first pass gate transistor with the first pull down transistor and a data line complement is coupled to a node coupling the second pass gate transistor with the second pull down transistor. A current cut-off device cuts off parasitic current from flowing through the first pass gate transistor and the first pull down transistor and through the second pass gate transistor and the second pull down transistor.

Low power sense amplifier for static random access memory

Disclosed is a ROM memory device including a plurality of rows and columns of memory cells, each memory cell including a bit line pair and a transistor to store two bits of data therein, and a virtual ground line disposed between adjacent pairs of bit line pairs, wherein the bit line pair and virtual ground line are used to read data stored in the memory cells.

1T compact ROM cell with dual bit storage for high speed and low voltage

A sense amplifier for a static random access memory (SRAM) is described. In one embodiment, a first pass gate transistor is driven by a bit line true associated with an SRAM cell. A second pass gate transistor is driven by a bit line complement associated with the SRAM cell. A first pull down transistor is coupled to the first pass gate transistor and a second pull down transistor is coupled to the second pass gate transistor. A data line true is coupled to a node coupling the first pull down transistor with the first pass gate transistor. A data line complement is coupled to a node coupling the second pull down transistor with the second pass gate transistor.

Sense amplifier for static random access memory with a pair of complementary data lines isolated from a corresponding pair of complementary bit lines

A dynamic wordline assist circuit for improving performance of an SRAM. An SRAM is disclosed that includes a plurality of memory cells, wherein each memory cell is coupled to a wordline and a pair of bitlines; and a wordline assist circuit coupled to the wordline, wherein the wordline assist circuit includes a first input for activating the wordline assist circuit during a read or write cycle and includes a second input for deactivating the wordline assist circuit during the read or write cycle after a delay.

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Bengaluru, India

Pankaj Agarwal