Industrial Technology Research Institute

Pang-Shiu Chen

Chee-Wee Liu

Heng-Yuan Lee

Lih-Juann Chen

Sheng-Wei Lee

Yu-Sheng Chen

Ching-Chiun Wang

Tai-Yuan Wu

Yen-Ya Hsu

Ching-Chih Hsu

Frederick Chen

Kao-Feng Liao

Yang-Tai Tseng

Shin-Chi Lu

Buo-Chin Hsu

A resistive random access memory and a method for fabricating the same are provided. The method includes forming a bottom electrode on a substrate; forming a metal oxide layer on the bottom electrode; forming an oxygen atom gettering layer on the metal oxide layer; forming a first top electrode sub-layer on the oxygen atom gettering layer; forming a second top electrode sub-layer on the first top electrode sub-layer, wherein the first top electrode sub-layer and the second top electrode sub-layer comprise a top electrode; and subjecting the metal oxide layer and the oxygen atom gettering layer to a thermal treatment, driving the oxygen atoms of the metal oxide layer to migrate into and react with the oxygen atom gettering layer, resulting in a plurality of oxygen vacancies within the metal oxide layer.

Resistive random access memory and method for fabricating the same

A control method for at least one memory cell is disclosed. The memory cell includes a transistor and a resistor. The resistor is connected to the transistor in series between a first node and a second node. In a programming mode, the memory cell is programmed. When it is determined that the memory cell has been successfully programmed, impedance of the memory cell is in a first state. When it is determined that the memory cell has not been successfully programmed, a specific action is executed to reset the memory cell. The impedance of the memory cell is in a second state after the step resetting the memory cell. The impedance of the memory cell in the second state is higher than that of the memory cell in the first state.

Control method for memory cell

A control method for at least one memory cell is disclosed. The memory cell includes a transistor and a resistor. The resistor is connected to the transistor between a first node and a second node. In a programming mode, the memory cell is programmed. The step of programming the memory cell includes providing a first controlling voltage to a gate of the transistor, providing a first setting voltage to the first node, and providing a second setting voltage to the second node. When it is determined that the memory cell has been successfully programmed, a specific action is executed.

A method for growing strained Si layer and relaxed SiGe layer with multiple Ge quantum dots (QDs) on a substrate is disclosed. The method can reduce threading dislocation density, decrease surface roughness of the strained silicon and further shorten growth time for forming epitaxy layers than conventional method. The method includes steps of: providing a silicon substrate, forming a multiple Ge QDs layers; forming a layer of relaxed SiGe; and forming a strained silicon layer in subsequence; wherein x is greater than 0 and less than 1.

Strained silicon forming method with reduction of threading dislocation density

A method to fabricate patterned strain-relaxed SiGe epitaxial with threading dislocation density control is provided. An ion-implanting area is first defined on a silicon substrate, and then proceeds ion-implanting. Finally, a buffer layer and a SiGe epitaxial layer are deposited. According to the disclosure, an active area and a non-active area are defined through ion-implanting. Therefore, the threading dislocation occurring in the active area concentrates in the non-active area, and the density of the threading dislocation is lowered. Furthermore, the performance of the semiconductor is also enhanced.

Method to fabricate patterned strain-relaxed SiGe epitaxial with threading dislocation density control

A construction of thin strain-relaxed SiGe layers and method for fabricating the same is provided. The construction includes a semiconductor substrate, a SiGe buffer layer formed on the semiconductor substrate, a Si(C) layer formed on the SiGe buffer layer, and an relaxed SiGe epitaxial layer formed on the Si(C) layer. The Si(C) layer is employed to change the strain-relaxed mechanism of the relaxed SiGe epitaxial layer formed on the Si(C) layer. Therefore, a thin relaxed SiGe epitaxial layer with low threading dislocation density, smooth surface is available. The fabricating time for fabricating the strain-relaxed SiGe layers is greatly reduced and the surface roughness is also improved.

Construction of thin strain-relaxed SiGe layers and method for fabricating the same

The present invention discloses a method for fabricating multiple-thickness insulator layers via strain field generated by stress. The strain field is used for alternating a develop mechanism of insulator layers on the quantum dots. By forming the multiple-thickness insulator layers at various developing rates, not only leakage current is prevented, but also components are kept isolated in the nano-electronics components. In nano-electronics manufacturing, the method for fabricating multiple-thickness insulator layers results in both better product reliability and the yield rate. It is potential for integral circuit manufacturing.

Growing community of inventors

Hsinchu, Taiwan

Pang-Shiu Chen