Institute of Microelectronics

Other

Singapore Science Park Ii

Pang Dow Foo

Uppili Sridhar

Hanhua Feng

Jun Cai

Narayanan Balasubramanian

Shuming Xu

Mnoon Yan Loke

Bai Xu

Rakesh Kumar

Zhe Wang

Yu Jau Chen

Quanbo Zou

Helmut F Schlaak

Victor Samper

Qingxin Zhang

Leong Tee Koh

Joon Mo Kang

Haijun Zhao

Minghui Gao

Abhijit Bandyopadhyay

Lian Jun Liu

Kay Krupka

Dirk Wagenaar

Shaoyu Wu

The invention relates to a method of making an integrated circuit inductor that comprises a silicon substrate and an oxide layer on the silicon substrate. In one aspect, the method comprises depositing an inductive loop on the oxide layer, and making a plurality of apertures in the oxide layer beneath the inductive loop. The method also comprises providing a plurality of bridges adjacent the apertures and provided by portions of the oxide layer between an inner region within the inductive loop and an outer region of the oxide layer without the inductive loop, the inductive loop being supported on the bridges. The method comprises forming a trench in the silicon substrate beneath the bridges, to provide an air gap between the inductive loop and the silicon substrate.

Method of making an integrated circuit inductor wherein a plurality of apertures are formed beneath an inductive loop

When using hot alkaline etchants such as KOH, the wafer front side, where various devices and/or circuits are located, must be isolated from any contact with the etchant. This has been achieved by using two chambers that are separated from each other by the wafer that is to be etched. Etching solution in one chamber is in contact with the wafer's back surface while deionized water in the other chamber contacts the front surface. The relative liquid pressures in the chambers is arranged to be slightly higher in the chamber of the front surface so that leakage of etchant through a pin hole from back surface to front surface does not occur. As a further precaution, a monitor to detect the etchant is located in the DI water so that, if need be, etching can be terminated before irreparable damage is done.

Apparatus and process for bulk wet etch with leakage protection

A microstructure relay is provided, having a body that includes upper and lower portions. The lower portion is formed from a substrate, and the upper portion is formed on the substrate to avoid bonding of the lower portion to the upper portion. A support member is fixed to the body at a first end of the support member to form a cantilever, wherein an upper surface of the support member and a lower surface of the upper portion of the body form a cavity. A first contact region is located on the upper surface at a second end of the support member. The first contact region comprises a first contact, wherein pivoting the support member toward the lower surface causes the first contact to be electrically coupled to a counter contact.

Micro-relay

A method is described for reducing dishing in a chemical mechanical polishing process performed on a semiconductor wafer having a dielectric layer with trenches and a copper layer deposited over the dielectric layer and filling the trenches in the dielectric layer. The method comprises steps of removing excess copper above the plane of the dielectric surface using a main polishing operation, whereby copper residues are formed above the plane of the dielectric surface, and applying chemical treatment to the surface of the semiconductor wafer in the initial stage of an overpolishing operation, wherein a protective layer over the copper residues and surfaces of copper-filled trenches is formed. The method further comprises steps of removing the copper residues and protective layer thereon above the plane of the dielectric layer in the overpolishing operation, and removing the protective layer over the surfaces of the copper-filled trenches in the overpolishing operation.

Method for reducing dishing in chemical mechanical polishing

A novel silicon RF LDMOSFET structure based on the use of a stacked LDD, is disclosed. The LDD has been modified from a single layer of N type material to a stack of three layers. These are upper and lower N type layers with a P type layer between them. The upper N type layer is heavily doped to reduce the on-resistance of the device, while the lower N type layer is lightly doped to reduce the output capacitance, thereby improving the high frequency performance. The middle P layer is heavily doped which allows it to bring about pinch-off of the two N layers, thereby raising the device's breakdown voltage. A process for manufacturing the device, as well as experimental data concerning its performance are also given.

Stacked LDD high frequency LDMOSFET

A method of forming bonds between similar and dissimilar material surfaces particularly the surfaces of silicon wafers having various devices disposes thereon, wherein such bonds can be formed at room temperature and do not require the application of high pressures or voltages. The bonding material is polydimethylsiloxane, which is transparent and bio-compatible.

Room temperature wafer-to-wafer bonding by polydimethylsiloxane

An inductor has a spiral aluminum track deposited on an oxide layer over a silicon substrate. The substrate is etched away to form a trench, which extends around beneath the track and provides an air gap having a low dielectric constant. The oxide layer has an inner region within the track, an outer region outside the track and a bridging region extending between the other regions. The bridging region is comprised of intact bridges and gaps therebetween, which are open to the trench and through which an etchant has access to the silicon substrate to form the trench by etching.

Integrated circuit inductor

The current invention teaches the use of e-beam patterning techniques for forming contact and via holes of diameter less than about 0.15 microns down to 0.05 microns. E-beam lithography has higher resolution (down to 30-50 nanometers) as compared to 130-150 nanometer when using deep ultra violet (DUV) photolithography patterning techniques. In addition the invention uses a mix and match approach by employing a conventional I-line, or deep UV, resist to form the trench pattern and e-beam lithography tools to form the contact and vial hole patterns. A simplified process scheme is developed where contact/via holes are formed first on solvent developable e-beam resist and the trench pattern is formed on aqueous developable photoresist coated on top of the e-beam resist.

Bi-layer resist process for dual damascene

A bipolar complementary metal oxide semiconductor device has a c-well fabricated using profile engineering (a multi-energy implant using accurate dosages and energies determined by advance simulation) to provide a higher c-well implant dose while creating a narrow region with relatively low concentration in the collector depletion range to avoid low base-collector breakdown. This achieves a much lower collector series resistance to pull-up a frequency response, a collector sheet resistance which can be as low as 150 &OHgr;/sq., and f may be increased to 20 GHz or higher.

High speed, low cost BICMOS process using profile engineering

A pressure sensor fabricated onto a substrate using conventional CMOS fabrication processes. The pressure sensor is built on a substrate having a first conductivity type and has defined in it a well of an opposite conductivity type. This well defines a membrane. Resistors are diffused into the well. Source/drain regions are provided for leadouts for the resistors. An n-cap is provided for the resistors. Metalization contacts may be provided to connect the membrane to a positive bias during a membrane etching process. A cavity is provided on the underside of the substrate through which pressure is applied to the membrane. Signal conditioning circuitry, such as an operational amplifier, may also be fabricated on the same substrate preferably using the same IC processes.

CMOS compatible integrated pressure sensor

An apparatus for sensing an applied force comprising a deflectable bridge, formed in a substrate and spanning a recessed area. The deflectable bridge also has a sensing element. The force is applied to the bridge and in response thereto, an output characteristic of the sensing element changes in proportion to the magnitude of the applied force. The apparatus can further comprise a sensing bump in contact with the bridge, wherein the force is applied to the bridge through the sensing bump.

Growing community of inventors

Singapore, Singapore

Pang Dow Foo