Rambus Inc.

Panduka Wijetunga

Aws Shallal

Gaurav Bawa

Abhishek Desai

Cosmin Iorga

Catherine Chen

Srinivas Satish Babu Bamdhamravuri

Mo Zhang

Joey M Esteves

Marcial Chua

Dhiraj Kumar

Philip Lu

An integrated circuit including a buck converter having an integrator and a shunt resistor is described. The buck converter may operate in a continuous conduction mode (CCM) and a discontinuous conduction mode (DCM). The integrator may be coupled to the buck converter to generate an output voltage based on adjustment of a detected voltage across a load of the buck converter within range of a reference voltage. The shunt resistor may be coupled to the integrator configured to maintain the output voltage of the integrator during the DCM.

Implementing a buck converter supporting automatic continuous conduction mode and discontinuous conduction mode

A power converter includes a plurality of power stages configured to generate an output current that has an output voltage, based on an input current that as an input voltage. The plurality of power stages comprises a first power stage and one or more additional power stages. The power converter also includes a control circuit coupled to the plurality of power stages. The control circuit is configured to periodically turn on each of the plurality of power stages. The control circuit determines a respective time delay between turning on the first power stage and turning on each of the one or more additional power stages based on a switching time-period of the first power stage.

Constant-on-time power converter with adaptive interleaving

A phase-locked loop or delay locked loop provides a coarse alignment between an input clock and an output clock. A latch receiver circuit provides an indicator of a delay error between the input clock and the output clock. The delay error is used by a control circuit or state machine to adjust a fine delay that affects the output clock signal timing relative to the input clock signal. The fine delay is adjusted to minimize the timing difference between the output clock signal and the input clock signal.

Clock buffer

Disclosed are techniques for a power management integrated circuit (PMIC) to support a power-up sequence from a powered-down state to a powered-up state when both a main supply voltage and a backup supply voltage are present or when only the backup supply voltage is present. The PMIC may monitor the two supply voltages to identify the supply voltages that are present. The PMIC may be configured with a power-up initialization mode of operation through an EFUSE/MTP register, including a first bit to control power up of a voltage regulator of the PMIC with the main supply voltage or the backup supply voltage. Another bit may control power up of the voltage regulator with the backup supply voltage in the dual-supply or the single-supply configuration. The PMIC may execute one of four power-up sequences based on the monitored status of the supply voltages and the configured power-up initialization mode of operation.

Power management integrated circuit device having multiple initialization/power up modes

A power-management integrated circuit (PMIC) is installed on a memory module to optimize power use among a collection of memory devices. The PMIC includes external power-supply nodes that receive relatively high and low supply voltages. Depending on availability, the PMIC uses one or both of these supply voltages to generate a managed supply voltage for powering the memory devices. The PMIC selects between operational modes for improved efficiency in dependence upon the availability of one or both externally provided supply voltages.

Methods and circuits for power management of a memory module

A clocking architecture for a memory module is configurable to independently select either rising or falling edges of an input clock as respective references for generation of an internal clock and an output clock. The clocking architecture supports reference edge selection in both a single data rate (SDR) mode and a double data rate (DDR) mode while maintaining a fixed phase relationship between the input clock and the output clock regardless of the reference edge selection.

Clocking architecture supporting multiple data rates and reference edge selection

A memory controller conveys a clock signal with command and address signals to a registered clock driver (RCD) on a memory module. A controller-side chip interface on the RCD supports both source-synchronous and filtered clocking for receipt of the command and address signals, the selection between the two clocking schemes dependent upon the noise environment impacting the clock and command/address signals. If the noise is predominantly correlated, then the chip interface is placed in a source-synchronous clocking mode. If the noise is predominantly uncorrelated, then the chip interface is placed in a filtered clocking mode that filters out uncorrelated noise from the clock signal.

Circuits and methods for sample timing in correlated and uncorrelated signaling environments

A binary receiver combines a fast amplifier with a relatively slow amplifier for noise rejection. Both the fast and slow amplifiers employ hysteresis. The fast amplifier has relatively lower hysteresis, meaning that its sensitivity is a less effected by prior data values but more susceptible to glitch-induced errors. Conversely, the slow amplifier has relatively higher hysteresis and rejects glitches but introduces undesirable signal-propagation delays. A state machine taking input from both amplifiers allows the receiver to filter glitches without incurring a significant data-propagation delay.

Receiver with improved noise immunity

Push-pull integrated circuit output drivers may interfere with communication by other entities on a bus when an integrated circuit is powered down. When there is no power and/or when the bonding pad is externally driven above the internal supply voltage, the substrate/body/well of the p-channel field effect transistor (PFET) of the output driver is biased to prevent its drain diode from becoming forward biased thereby preventing interference with communication on the bus. Also, when there is no power, driver is powered down or pull up is disabled, the gate of the driver PFET is driven to a voltage that ensures the driver PFET remains off when the bonding pad is externally driven above the internal supply voltage.

Growing community of inventors

Thousand Oaks, CA, United States of America

Panduka Wijetunga