International Business Machines Corporation

Other

Ebara Corporation

Panayotis Constantinou Andricacos

Hariklia Deligianni

Wilma Jean Horkans

John Michael Cotte

Cyprian Emeka Uzoh

Cyril Cabral, Jr

Kenneth Parker Rodbell

John Owen Dukovic

Keith Thomas Kwietniak

Katherine Lynn Saenger

Lubomyr Taras Romankiw

Peter Stevens Locke

Daniel C Edelstein

Christopher Vincent Jahnes

Richard Paul Volant

Kenneth Jay Stein

John Harold Magerlein

Jennifer L Lund

L Paivikki Buchwalter

David Edward Kotecki

Mahadevaiyer Krishnan

Chao-Kun Hu

Lynne Marie Gignac

James Edward Fluegel

Philippe Mark Vereecken

Alfred Grill

Kevin Shawn Petrarca

Emanuel Israel Cooper

Robert Allen Groves

Fenton Read McFeely

Christopher Carr Parks

David Earle Seeger

Erick G Walton

Milan Paunovic

Steven H Boettcher

Kwong-Hon Wong

Ping-Chuan Wang

Soon-Cheon Seo

Timothy Dooling Sullivan

Sandra Guy Malhotra

Scott Kevin Reynolds

Shyng-Tsong Chen

Sung Kwon Kang

Roy Arthur Carruthers

James M Harper

Madhav Datta

Dale J Pearson

Wei-Tsu Tseng

King-Ning Tu

James Anthony Tornello

Matteo Flotta

Michael Meixner

Bojan Petek

Dean S Chung

Jei-Wei Chang

Kirk G Berridge

Roger Yen-Luen Tsai

Sampath Purushothaman

Timothy Joseph Dalton

Alejandro Gabriel Schrott

Andrew Herbert Simon

Laertis Economikos

Jonathan David Reid

Conal Eugene Murray

Roger Allan Quon

Vishnubhai Vitthalbhai Patel

Leathen Shi

Ho-Ming Tong

Michael Wayne Lane

Evan E Patton

Mizuki Nagai

Hiroyuki Kanda

Darryl D Restaino

Tien-Jen Cheng

Gregory Costrini

John Gerard Gaudiello

Satoru Yamamoto

Randolph F Knarr

Gangadhara Swami Mathad

Cornelia Kang-I Tsang

Michelle Leigh Steen

Robert P Westerfield, Jr

Jonathan H Griffith

Ronald Dean Goldblatt

Raul E Acosta

Philippe M Vereecken

David E Eichstadt

Daniel Guidotti

Keiichi Kurashina

Ryoichi Kimizuka

James H Comfort

Robert W Hitzfeld

William E Corbin, Jr

I-Chia H Chang

Frank A Spera

Judith D Olsen

Robert M Browne

Brett Baker

Phillipe Vereecken

Moritz Branger

A method of forming an inductor. The method including: (a) forming a dielectric layer on a top surface of a substrate; after (a), (b) forming a lower trench in the dielectric layer; after (b), (c) forming a resist layer on a top surface of the dielectric layer; after (c), (d) forming an upper trench in the resist layer, the upper trench aligned to the lower trench, a bottom of the upper trench open to the lower trench; and after (d), (e) completely filling the lower trench and at least partially filling the upper trench with a conductor in order to form the inductor.

Method of fabricating a high Q factor integrated circuit inductor

An improved method of stabilizing wet chemical baths is disclosed. Typically such baths are used in processes for treating workpieces, for example, plating processes for plating metal onto substrates. In particular, the present invention relates to copper plating baths. More particularly, the present invention relates to the stability of copper plating baths. More particularly, the present invention relates to prevention of void formation by monitoring the accumulation of deleterious by-products in copper plating baths.

Void-free damascene copper deposition process and means of monitoring thereof

A method of forming an inductor. The method includes: forming a dielectric layer on a substrate; forming a lower trench in the dielectric layer; forming a liner in the lower trench and on the dielectric layer; forming a Cu seed layer over the liner; forming a resist layer on the Cu seed layer; forming an upper trench in the resist layer; electroplating Cu to completely fill the lower trench and at least partially fill the upper trench; removing the resist layer; selectively forming a passivation layer on all exposed Cu surfaces; selectively removing the Cu seed layer from regions of the liner; and removing the thus exposed regions of the liner from the dielectric layer, wherein a top surface of the inductor extends above a top surface of the dielectric layer, the passivation layer remaining on regions of sidewalls of the inductor above the top surface of the dielectric layer.

A semiconductor micro-electromechanical system (MEMS) switch provided with noble metal contacts that act as an oxygen barrier to copper electrodes is described. The MEMS switch is fully integrated into a CMOS semiconductor fabrication line. The integration techniques, materials and processes are fully compatible with copper chip metallization processes and are typically, a low cost and a low temperature process (below 400&#xb0; C.). The MEMS switch includes: a movable beam within a cavity, the movable beam being anchored to a wall of the cavity at one or both ends of the beam; a first electrode embedded in the movable beam; and a second electrode embedded in an wall of the cavity and facing the first electrode, wherein the first and second electrodes are respectively capped by the noble metal contact.

Method of forming noble metal contacts

A plating method is capable of mechanically and electrochemically preferentially depositing a plated film in fine interconnect recesses such as trenches and via holes, and depositing the plated film to a flatter surface. The plating method including: disposing a substrate having fine interconnect recesses such that a conductive layer faces an anode; disposing a porous member between the substrate and the anode; filling a plating solution between the substrate and the anode; and repeating a process of holding the conductive layer and the porous member in contact with each other and moving the conductive layer and the porous member relatively to each other, a process of passing an electric current between the conductive layer and the anode while keeping the conductive layer still with respect to the porous member, and a process of stopping the supply of the electric current between the conductive layer and the anode.

Plating apparatus and plating method

Interconnect structures with copper conductors being at least substantially free of internal seams or voids are obtained employing an electroplating copper bath containing dissolved cupric salt wherein the concentration of the salt is at least about 0.4 molar and up to about 0.5 molar concentration of an acid. Also provided are copper damascene structures having an aspect ratio of greater than about 3 and a width of less than about 0.275 &#x3bc;m and via openings filled with electroplated copper than is substantially free of internal seams or voids.

Electroplated copper interconnection structure, process for making and electroplating bath

A microelectromechanical switch including: at least one pair of actuator electrodes; at least one input electrode and at least one output electrode for input and output, respectively, of a radio frequency signal; and a beam movable by an attraction between the at least one pair of actuator electrodes, the movable beam having at least a portion electrically connected to the at least one input electrode and to the at least one output electrode when moved by the attraction between the at least one pair of actuator electrodes to make an electrical connection between the at least one input and output electrodes; wherein the at least one pair of actuator electrodes are electrically isolated from each of the at least one input and output electrodes. The microelectromechanical switch can be configured in single or multiple-poles and/or single or multiple throws.

Micro-electro-mechanical RF switch

Noble metal contacts for micro-electromechanical switches

Patterned copper structures are fabricated by selectively capping the copper employing selective etching and/or selective electroplating in the presence of a liner material. Apparatus for addressing the problem of an increased resistive path as electrolyte during electroetching and/or electroplating flows from the wafer edge inwards is provided.

Selective capping of copper wiring

An inductor and a method of forming and the inductor, the method including: (a) providing a semiconductor substrate; (b) forming a dielectric layer on a top surface of the substrate; (c) forming a lower trench in the dielectric layer; (d) forming a resist layer on a top surface of the dielectric layer; (e) forming an upper trench in the resist layer, the upper trench aligned to the lower trench, a bottom of the upper trench open to the lower trench; and (f) completely filling the lower trench at least partially filling the upper trench with a conductor in order to form the inductor. The inductor including a top surface, a bottom surface and sidewalls, a lower portion of said inductor extending a fixed distance into a dielectric layer formed on a semiconductor substrate and an upper portion extending above said dielectric layer; and means to electrically contact said inductor.

High Q factor integrated circuit inductor

Flared and non-flared metallized deep vias having aspect ratios of about 2 or greater are provided. Blind vias have been fabricated in silicon substrates up to a depth of about 300 microns, and flared through vias have been fabricated up to about 750 microns, the approximate thickness of a silicon substrate wafer, enabling the formation of electrical connections at either or both ends of a via. In spite of the depth and high aspect ratios attainable, the etched vias are completely filled with plated copper conductor, completing the formation of deep vias and allowing fuller use of both sides of the substrate.

Deep filled vias

A method of creating a multi-layered barrier for use in an interconnect, a barrier for an interconnect, and an interconnect including the barrier are disclosed. The method includes creating the multi-layered barrier in a recess of the device terminal by use of a single electroplating chemistry to enhance protection against voiding and de-lamination due to the diffusion of copper, whether by self-diffusion or electro-migration. The barrier includes at least a first layer of nickel-rich material and a second layer of copper-rich material. The barrier enables use of higher current densities for advanced complementary metal-oxide semiconductors (CMOS) designs, and extends the reliability of current CMOS designs regardless of solder selection. Moreover, this technology is easily adapted to current methods of fabricating electroplated interconnects such as C4s.

Barrier for interconnect and method

A method for plating copper conductors on an electronic substrate and devices formed are disclosed. In the method, an electroplating copper bath that is filled with an electroplating solution kept at a temperature between about 0&#xb0; C. and about 18&#xb0; C. is first provided. A copper layer on the electronic substrate immersed in the electroplating solution is then plated either in a single step or in a dual-step deposition process. The dual-step deposition process is more suitable for depositing copper conductors in features that have large aspect ratios, such as a via hole in a dual damascene structure having an aspect ratio of diameter/depth of more than &#x2153; or as high as 1/10. Various electroplating parameters are utilized to provide a short resistance transient in either the single step deposition or the dual-step deposition process. These parameters include the bath temperature, the bath agitation, the additive concentration in the plating bath, the plating current density utilized, the deposition rate of the copper film and the total thickness of the copper film deposited.

Method for plating copper conductors and devices formed

A conductive material is electroplated onto a platable resistive metal barrier layer(s) employing a plating bath optionally comprising a super filling additive and a suppressor, and by changing the current or voltage as a function of the area of plated metal. A structure is also provided that comprises a substrate, a platable metal barrier layer(s) located on the substrate and a relatively continuous uniform electroplated layer of a conductive material located on the platable resistive metal barrier layer.

Method for electroplating on resistive substrates

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Croton-on-Hudson, NY, United States of America

Panayotis Constantinou Andricacos