Samsung Electronics Co., Ltd.

Pan-Suk Kwak

Chan-Ho Kim

Bong-Soon Lim

Hong-soo Jeon

Kyung-Hwa Yun

Dong-kil Yun

Sung-Hoon Kim

Ki-Tae Park

Yoon-Hee Choi

Sang-won Shim

Chul-Jin Hwang

An-Soo Park

Seok-Jun Ham

A non-volatile memory includes a first semiconductor layer vertically stacked on a second semiconductor layer and including a first memory group, a second memory group, a third memory group and a fourth memory group. The second semiconductor layer includes a first region, a second region, a third region and a fourth region respectively underlying the first memory group, second memory group, third memory group and fourth memory group. The first region includes one driving circuit connected to memory cells of one of the second memory group, third memory group and fourth memory group through a first word line, and another driving circuit connected to memory cells of the first memory group through a first bit line, wherein the first word line and first bit line extend in the same horizontal direction.

Non-volatile memory

A non-volatile memory device may include a first semiconductor layer including a peripheral region, the peripheral region including one or more peripheral transistors on a lower substrate. The non-volatile memory device may further include a second semiconductor layer on the peripheral region, the second semiconductor layer including an upper substrate, the second semiconductor layer further including a memory cell array on the upper substrate. The upper substrate may include a first upper substrate on the first semiconductor layer, a first layer on the first upper substrate, and a second upper substrate on the first layer.

Non-volatile memory devices and methods of fabricating the same

A three-dimensional (3D) nonvolatile memory includes a stacked structure that includes a plurality of conductive layers that alternate with and are spaced apart from each other by a plurality of interlayer insulating layers. The stacked structure includes a first cell region, a second cell region spaced apart from the first cell region, and a connection region between the first cell region and the second cell region. The connection region includes a first step portion that contacts the first cell region and has a stepped shape that descends in a direction approaching the second cell region, a second step portion that contacts the second cell region and has a stepped shape that descends in a direction approaching the first cell region, and a connection portion that connects the first cell region and the second cell region.

Nonvolatile memory device

A vertical memory device and a method of manufacturing the same, the device including a cell array including cell regions spaced apart from each other in a second direction, each cell region including a regularly arranged plurality of vertical channels; bit-lines extending in the second direction, the bit-lines being spaced apart from each other in a first direction crossing the second direction; and bit-line contacts respectively electrically connecting the vertical channels and the bit-lines, wherein each cell region includes a sub isolation region configured to electrically isolate the cell region in the second direction, the sub isolation region extending in the first direction, the vertical channels are classified into a plurality of types according to a distance from the sub isolation region in the second direction in each cell region, and the bit-line contacts are configured to electrically connect each bit-line to at least two vertical channels having different types.

Vertical memory devices and methods of manufacturing vertical memory devices

A non-volatile memory device is provided as follows. A substrate has a peripheral circuit. A first semiconductor layer is disposed on the substrate. The first semiconductor layer includes a memory cell region. A first gate structure is disposed on the first semiconductor layer. The first gate structure includes a plurality of first gate electrodes stacked in a perpendicular direction to the first semiconductor layer and a plurality of vertical channel structures penetrating the plurality of first gate electrodes. The first gate structure is arranged in the memory cell region. A second gate structure is disposed on the substrate. The second gate structure includes a plurality of second gate electrodes stacked in the perpendicular direction to the first semiconductor layer. The second gate structure is arranged outside the memory cell region.

Non-volatile memory device with first gate structure in memory cell region and second gate structure in peripheral circuit region and non-volatile memory system including the same

A nonvolatile memory device including memory blocks, a pre-decoder, and a row decoder is disclosed. Each of the memory blocks has a plurality of memory cells. The pre-decoder includes a multiplexer and negative level shifters. The multiplexer is configured to generate multiplexing signals in response to address signals. Each of the negative level shifters is configured to generate a converted multiplexing signal corresponding to a respective multiplexing signal by converting a multiplexing signal having a ground voltage into a converted multiplexing signal having a first negative voltage. The row decoder is configured to select at least one of the memory blocks in response to the converted multiplexing signals.

Nonvolatile memory device providing negative voltage

The disclosure is of a memory device using an address transition signal and having sense amplifiers, sense amplifier latch circuits, and a data output buffer, including: a circuit for generating a plurality of control signals for the sense amplifiers and latch circuits; and a circuit for inhibiting a generation of a control signal which causes a transfer from the sense amplifier to the data output buffer in the case of an abnormal address transition pulse signal that may be noisy or of a shortened duration. An invalid data transfer through the latch circuit can be prevented from a noise-included address transition signal.

Growing community of inventors

Seoul, South Korea

Pan-Suk Kwak