International Business Machines Corporation

Globalfoundries Inc.

Pamela Castalino

Toshiaki Kirihata

Harold Pilo

Amith Singhee

Shahid Ahmad Butt

Aditya Bansal

Derek H Leu

Sudesh Saroop

Dallas M Lea

Peter W Schneider

Joseph P Walko

A bitline circuit for embedded Multi-Time-Read-Only-Memory including a plurality of NMOS memory cells coupled to a plurality of wordlines in each row, bitlines in each column, and a source-line. More specifically, the bitline circuit controls a charge trap behavior of the target NMOS memory array by mode-dependent bitline pull-down circuit, thereby discharging the bitline strongly to GND to trap the charge effectively in a Programming mode, and discharge the bitline weakly to GND to develop a bitline voltage to detect the charge trap state. The mode dependent circuit is realized by using at least two NMOS to switch the device strength, using a pulsed gate control in a Read mode, or using analog voltage to limit the bitline current. The proposed method further includes a protection device, allowing all bitline control circuit using thin oxide devices. The bitline circuits having mode and bank access dependent bitline circuit further enables a single device memory array, by using two arrays, wherein said one of the array is used for reference to the other array using an open bitline architecture.

Bitline circuits for embedded charge trap multi-time-programmable-read-only-memory

Transistors are connected to ground outside of an SRAM array column. One transistor is connected from VSS to ground on the Q side of an SRAM cell. Another transistor is connected from VSS to ground on the Q' (Q complement) side of an SRAM cell. Each transistor is gated by is complementary bit line. The Q side transistor is gated by the BL&#x2032; (bit line complement, or 'BLC') line, and the Q&#x2032; side is gated by the BL line. The ground of the complement side is disconnected during a write operation to increase the performance of a state change during a write operation where a logical one is written to the Q node, thus improving write margin.

SRAM circuit with increased write margin

A method is disclosed for evaluating a model, characterized as being a computer executable device and circuit simulator. The method includes accepting measured parameters of devices, which devices are essentially identical with, or are actually from, a simulated circuit instance. The model is executed with adjusted input parameters to generate simulated values for properties of the circuit instance. These simulated values are compared with measured values of the same properties. The goodness of the model is determined based on the degree of direct, or statistical, agreement between the simulated and measured values.

Circuit-level validation of computer executable device/circuit simulators

Disclosed are embodiments of a method, a system and a program storage device for simulating electronic device performance as a function of process variations. In these embodiments, functions of a primary model parameter for each of multiple secondary model parameters across multiple different process conditions can be determined based on a relatively small number of target sets of device characteristics. These functions can then be used to augment a simulator so that during subsequent simulations of the electronic device over a wide range of varying process conditions, a change in a value for the primary model parameter will automatically result in corresponding changes in values for the secondary model parameters. By augmenting the simulation environment in this manner, the disclosed embodiments efficiently provide more robust simulation results over prior art techniques.

Method, system and program storage device for simulating electronic device performance as a function of process variations

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Hopewell Junction, NY, United States of America

Pamela Castalino