Intel Corporation

Maxtor Corporation

Inter Corporation

Pak-Lung Seto

Victor Lau

Naichih Chang

Nai-Chih Chang

William R Halleck

Gary Tsao

Vicky P Duerk

Luke L Chang

Deif N Atallah

Richard C Beckett

Suresh Chemudupati

Tracey L Gustafson

Devicharan Devidas

Eric J DeHaemer

Annie Foong

Satish L Rege

Robert L Sheffield

Kiran Vemula

Ankit Parikh

Martin M Massucci

Naichih (Neil) Chang

Deif Atallah

Yanqun Duerk

Gary Y Tsao

Techniques herein include systems and methods for driver-assisted BAR mapping that virtualize PCI functions, but without virtualizing the storage media itself. Such techniques make use of unused BARs (Base Address Registers) of a master (Operating system-facing) device to gain access to other PCIe logical instances, while still exposing only a single PCIe function (connection or channel) to system software. This technique provides a new concept of logical PCIe device instances through BAR mapping by making use of unused BARs to extend access to any number of PCIe instances or memory-mapped I/O devices behind a master device such that only a single PCIe function is exposed to system software. Embodiments can thus extend access to one or more additional storage devices through one level of BAR indirection. As a result, such techniques and embodiments enable the multiplication of storage capacity and performance through the aggregation of multiple, similar hardware components.

Driver-assisted base address register mapping

Link level load balancing is provided based on time utilization of a link or workload utilization of a device. Time utilization achieves load balancing by giving each device the same amount of connection time to perform Input/Output tasks. Workload utilization achieves load balancing by managing a number of frames or bytes transmitted to each device.

Load balancing in a storage system

According to one embodiment of the invention, a method comprises measuring memory access latency for a prefetch cycle associated with a transmission of data from a memory device to a destination device such as a storage device. Hereafter, the prefetch rate is dynamically adjusted based on the measured memory access latency.

System and method for dynamic data prefetching

An initial configuration is maintained assigning multiple local interfaces to one initial local address. For each local interface, a remote address of a remote interface on at least one remote device to which the local interface connects is received. The initial local address is used to identify the local interfaces assigned to the initial local address in response to receiving a same remote address for each remote interface connected to the local interfaces assigned the initial local address.

Addresses assignment for adaptor interfaces

An embodiment of the present invention is a technique to process a plurality of I/O sequences associated with a storage device. A task context pre-fetch engine pre-fetches a task context from a task context memory based on a pre-fetch request. At least a multi-threaded transmit transport layer (T&#xd7;TL) processes the plurality of I/O sequences from an I/O pool simultaneously. The multi-threaded T&#xd7;TL generates the pre-fetch request and one or more frames from the plurality of I/O sequences. A switch fabric and controller routes the frame to a link layer associated with the storage device.

Multi-threaded transmit transport engine for storage devices

Methods of scheduling tasks in computer systems architectures are disclosed. In one aspect, a method may include comparing a connection address of a first node with a connection address of a second node, determining that the connection address of the first node matches the connection address of the second node, and scheduling tasks to the first and second nodes based, at least in part, on the determination. Apparatus to implement task scheduling, and systems including the apparatus are also disclosed.

Task scheduling to devices with same connection address

According to one embodiment, a host bus adapter (HBA) is disclosed. The HBA includes one or more link layer engines, one or more ports, each of the one or more ports associated with one of the one or more link layer engines and token passing logic having a shift register associated with each of the one or more link layer engines. A first link layer engine enables a first storage device coupled to an associated port to spin-up whenever the first link layer engine detects that a first shift register has a first value.

Hard disk drive staggered spin-up mechanism

According to one embodiment, a device is disclosed. The device includes a first protocol engine (PE) to process tasks to be forwarded to a first remote node, a remote node search unit (RNSU) having a three-dimensional (3-D) task list corresponding to tasks to be forwarded to the two or more sub-nodes, and a connection pointer to maintain a connection between the first PE and the first remote node.

Remote node list searching mechanism for storage task scheduling

A method, computer program product, system (including a circuit card), and integrated circuit for initializing a buffer pool, such that the buffer pool includes a plurality of data buffers available for use during a plurality of I/O transfers. In response to the initiation of a first I/O transfer concerning a first data portion being transferred from a first data source to a first data target, the first data portion is written to a first portion of the plurality of data buffers. The first data portion is transferred to the first data target, and the first portion of the plurality of data buffers is released back to the buffer pool for use during one or more subsequent I/O transfers.

Dynamic memory buffer allocation method and system

According to one embodiment, an apparatus is disclosed. The apparatus includes a port having a plurality of lanes, a plurality of protocol engines. Each protocol engine is associated with one of the plurality of lanes, and processes tasks to be forwarded to a plurality of remote nodes. The apparatus also includes a first port task scheduler (PTS) to manage the tasks to be forwarded to the one or more of the plurality of protocol engines. The first PTS includes a register to indicate which of the plurality of protocol engines the first PTS is to support.

Method using port task scheduler

An expander device is configurable to identify itself as an end device and not an edge expander device. Other embodiments are also described and claimed.

Communications protocol expander

An apparatus according to one embodiment may include an integrated circuit. The integrated circuit may include a plurality communication channels. The integrated circuit may be is capable of communicating with at least one remote node external to the integrated circuit, via at least one of the communication channels, in accordance with at least one communication protocol. Each of said plurality of communication channels may provide a communication path between a host system and at least one remote node. The integrated circuit may be further capable of operating each communication channel independently of each other and independently of the host system. Of course, many alternatives, variations, and modifications are possible without departing from this embodiment.

Integrated circuit capable of independently operating a plurality of communication channels

Methods and apparatus for host-side Serial ATA Native Command Queuing (NCQ) tag management are disclosed. In one aspect, an exemplary apparatus may include a memory and an NCQ tag selection circuit in communication with the memory. The memory may store information for each of a plurality of different NCQ tag values. The information for each NCQ tag value may indicate whether or not a command having the NCQ tag value has been issued. The NCQ tag selection circuit may examine the information in the memory, and may select an NCQ tag value having information that indicates that a command having the NCQ tag value has not been issued. Systems and architectures including such apparatus are also disclosed.

Hardware oriented host-side native command queuing tag management

A device includes a task context controller, at least one transport engine connected to the task context controller, and at least one comparator connected to the transport engine. The comparator to compare a data offset from a receive frame with a current data offset and a result is used to determine frame processing order.

Hardware assisted receive channel frame handling via data offset comparison in SAS SSP wide port applications

A method according to one embodiment may include discovering at least one data block comprising logical block address information. The method may also include mapping logical block address information from a first domain into a second domain. Of course, many alternatives, variations, and modifications are possible without departing from this embodiment.

Growing community of inventors

Shrewsbury, MA, United States of America

Pak-Lung Seto