International Business Machines Corporation

Infineon Technologies Ag

Freescale Semiconductor,inc.

United Microelectronics Co.

United Microelectronics Corp.

Infineon Technologies North America Corp.

United Mircroelectronics Co.

Pak Leung

Robert C Wong

Ernst H Demm

Alexander M Hirsch

Stephen McConnell Gates

Lawrence Alfred Clevenger

David V Horak

Daniel C Edelstein

Shom Ponoth

Griselda Bonilla

Thomas M Shaw

Hans-Joachim Barth

Satyanarayana Venkata Nitta

Erdem Kaltalioglu

Edward Outlaw Travis, Jr

Kevin John Hess

Eric Gerhard Liniger

Brett P Wilkerson

Mark Hoinkis

Maxime Darnon

Scott K Pozder

Terry Grant Sparks

Gerald R Friese

Stephen Alan Cohen

Jie-Hua Zhao

David G Wontor

Samuel S S Choi

A method of annealing a semiconductor and a semiconductor. The method of annealing including heating the semiconductor to a first temperature for a first period of time sufficient to remove physically-adsorbed water from the semiconductor and heating the semiconductor to a second temperature, the second temperature being greater than the first temperature, for a period of time sufficient to remove chemically-adsorbed water from the semiconductor. A semiconductor device including a plurality of metal conductors, and a dielectric including regions separating the plurality of metal conductors, the regions including an upper interface and a lower bulk region, the upper interface having a density greater than a density of the lower bulk region.

Multiple step anneal method and semiconductor formed by multiple step anneal

A semiconductor interconnect architecture provides a reduction in the intersection of vias on the last layer ('VL') and holes in the last thin metal layer ('MLHOLE') without degradation of the product yield or robustness, or increases copper dishing. The mutation of some dense redundant VLs to MLHOLEs decreases the number of intersections between VLs and MLHOLEs.

Generation of metal holes by via mutation

A method and apparatus are described for fabricating an ultra low-k interconnect structure by depositing and curing a first via layer () of ultra low dielectric constant (ULK) material, depositing a second uncured trench layer () of the same ULK material, selectively etching a via opening () and trench opening () with a dual damascene etch process which uses a trench etch end point signal from the chemical differences between uncured trench layer () and the underlying cured via layer (), and then curing the second trench layer () before forming an interconnect structure () by filling the trench opening () and via opening () with an interconnection material so that there is no additional interface or higher dielectric constant material left behind.

Pseudo hybrid structure for low K interconnect integration

A reduction in the intersection of vias on the last layer ('VL') and holes in the last thin metal layer ('MLHOLE') can be achieved without degrading product yield or robustness or increasing copper dishing. The mutation of some dense redundant VLs to MLHOLEs decreases the number of intersections between VLs and MLHOLEs.

Method of producing a semiconductor interconnect architecture including generation of metal holes by via mutation

Disclosed is a process of an integration method to form an air gap in an interconnect. On top of a metal wiring layer on a semiconductor substrate is deposited a dielectric cap layer followed by a sacrificial dielectric layer and pattern transfer layers. A pattern is transferred through the pattern transfer layers, sacrificial dielectric layer, dielectric cap layer and into the metal wiring layer. The presence of the sacrificial dielectric layer aids in controlling the thickness and profile of the dielectric cap layer which in turn affects reliability of the interconnect.

Forming interconnects with air gaps

A technique for alleviating the problems of defects caused by stress applied to bond pads () includes, prior to actually making an integrated circuit (), adding dummy metal lines () to interconnect layers () to increase the metal density of the interconnect layers. These problems are more likely when the interlayer dielectrics () between the interconnect layers are of a low-k material. A critical area or force area () around and under each bond pad defines an area in which a defect may occur due to a contact made to that bond pad. Any interconnect layer in such a critical area that has a metal density below a certain percentage can be the cause of a defect in the interconnect layers. Any interconnect layer that has a metal density below that percentage in the critical area has dummy metal lines added to it.

Integrated circuit having structural support for a flip-chip interconnect pad and method therefor

In a semiconductor integrated circuit device, thermo-mechanical stresses on the vias can be reduced by introducing a stress relief layer between the vias and a hard dielectric layer that overlies the vias.

Stress-relief layer for semiconductor applications

Growing community of inventors

Cedar Park, TX, United States of America

Pak Leung