Quicklogic Corporation

Xilinx, Inc.

Paige A Kolze

David D Eaton

Weiguang Lu

James M Apland

William D Cox

James A Apland

David P Schultz

Andrew K Chan

Richard J Wong

Hua-Thye Chua

Andre N Stolmeijer

Chen Wei Tseng

Laurent Fabris Stadler

William W Stiehl

Carl M Stern

Kevin K Yee

Robert M Balzli, Jr

Patrick C McCarthy

Benjamin W Blair

Sudarshan Varshney

A circuit arrangement for enabling a partial reconfiguration of a circuit implemented in an integrated circuit device is described. The circuit arrangement comprises a plurality of circuit blocks, wherein each circuit block is configurable to implement a predetermined function and comprises a control circuit configured to receive a global enable signal and a plurality of global reconfiguration signals; and a routing network coupled to the plurality of circuit blocks for routing the global enable signal and the plurality of global reconfiguration signals to each circuit block of the plurality of circuit blocks; wherein each circuit block of the plurality of circuit blocks is configured to independently receive a local enable signal enabling a partial reconfiguration of the circuit in response to the plurality of global reconfiguration signals.

Circuit arrangement for and a method of enabling a partial reconfiguration of a circuit implemented in an integrated circuit device

Approaches for partially reconfiguring a frame are disclosed. In one approach, a circuit arrangement includes programmable resources, frames of configuration memory cells, and partial configuration control memory cells. Each frame includes a plurality of subsets of configuration memory cells, and each subset configures one of the programmable resources. Each partial configuration control memory cell is coupled to a respective one of the subsets. Responsive to a first partial bitstream that includes a quantity of configuration data for all the subsets of configuration cells of a first frame of the plurality of frames, each subset of the configuration memory cells of the first frame is configurable or not configurable responsive to the state of the associated partial configuration control memory cell.

Partially programming an integrated circuit using control memory cells

A configurable interface for an integrated circuit is described. The integrated circuit includes a first core, where the first core is an application specific circuit version of a Peripheral Component Interconnect Express ('PCIe') interface device. First configuration memory cells are associated with the first core, and the first configuration memory cells are for configuring the first core. The first configuration memory cells are programmable responsive to a first portion of a configuration bitstream, and the configuration bitstream is capable of including user-logic information for programming programmable logic of the integrated circuit.

Configurable interface

The programmable logic of a programmable device is sectioned into four logic regions. Each logic region includes logic elements and a programmable interconnect structure employing antifuses for programmably interconnecting selected ones of those logic elements. Programming conductors for supplying programming current to antifuses of a logic region extend across the logic region but do not extend across other logic regions. Similarly, programming control conductors that control programming transistors of the logic region extend across the logic region but do not extend across other logic regions. The programmable device structure allows four antifuses to be programmed simultaneously, one antifuse in each logic region. An antifuse can be selected for simultaneous programming from a logic region, irrespective of the other three antifuses that are or may be selected for simultaneous programming from the other three logic regions. Four programming current multiplexers and four programming buses are provided for each logic region so that the programming current that programs each antifuse flows from a separate input terminal. The resistance of the programming conductors is reduced by the use of parallel strips of metal in multiple metal layers.

Programming architecture for field programmable gate array

To protect logic module output devices from high voltages, logic modules are not powered during antifuse programming. In some embodiments, two separate power input terminals VCC1 and VCC2 are provided: power input terminal VCC1 being coupled to power the logic modules, and power input terminal VCC2 being coupled to power the programming control circuitry. Power terminal VCC1 is left floating or is grounded during antifuse programming such that the logic modules are not powered but such that the programming circuitry is powered during antifuse programming via the second power terminal VCC2. Logic module output protection transistors are not required nor is the associated charge pump. Because the logic module input devices are not powered, a current surge through the input devices on power up does not occur and an internal disable signal and associated circuitry is not required. In one embodiment, the field programmable gate array is made smaller because it has no internal disable signal and associated circuitry, no logic module output protection transistors, and no charge pump that operates during normal circuit operation. In embodiments, power input terminal VCC2 is a high voltage compatible power input terminal.

Protection of logic modules in a field programmable gate array during

A programmable integrated circuit (see FIG. 13) includes a plurality of routing resources including collinearly extending routing wire segments and a test circuit for testing the integrity of the routing wire segments. The routing resource structures include a plurality of unprogrammed antifuses disposed between routing wire segments and a plurality of transistors disposed electrically in parallel with a corresponding respective one of the antifuses. The test circuit has a common node that may be coupled to a selected one of the routing resource structures for testing. In test mode, the test circuit detects whether a current flows through the selected routing resource structure and in response provides either a digital low value or a digital high value on an output node.

Programmable integrated circuit having a test circuit for testing the

In a programmable device employing antifuses, first digital logic transistors the gates of which will experience a programming voltage Vpp have a greater gate insulator thickness than do second digital logic transistors the gates of which will not experience the programming voltage. The first digital logic transistors may be logic module input device transistors. The first digital logic transistors may be transistors coupled to an enable input lead where the enable input lead is couplable to a tie-high conductor or to a tie-low conductor depending on which of two antifuses is programmed.

Field programmable gate array having internal logic transistors with two

A field programmable gate array has columns of logic modules. A programming conductor used to conduct programming current to program antifuses of the field programmable gate array extends between two adjacent columns of logic modules. First wire segments extend from the programming conductor and toward the logic modules of a first of the two adjacent columns. Second wire segments extend the opposite direction from the programming conductor and toward logic modules of the second of the two adjacent columns. Programming current used to program antifuses disposed along the first wire segments as well as antifuses disposed along the second wire segments can be supplied from the same programming conductor that extends between the two columns of logic modules. The logic modules of the first column are mirrored versions of the logic modules of the second column.

Programmable integrated circuit having shared programming conductors

A programming architecture for a field programmable gate array (FPGA) employing antifuses is disclosed. To test the integrity of programming conductors, programming transistors, routing wire segments and a combinatorial portion of a logic module of the unprogrammed FPGA (see FIG. 16), a combination of digital logic values is supplied onto the inputs of the combinatorial portion in a test mode. A defect is determined to exist if the correct digital value is not then output by the combinatorial portion. The digital value output by the combinatorial portion is captured in the flip-flop of the logic module and is shifted out of the FPGA in a scan out test mode. A programming transistor, programming conductor and routing wire segment structure is also disclosed which facilitates such testing. In one embodiment (see FIG. 15), the gate of no programming transistor coupled to an output routing wire segment of the logic module (such as transistor 216) is permanently connected to the gate of any programming transistor coupled to an input routing wire segment of the logic module (such as transistors 200, 201 and 202).

Field programmable gate array having testable antifuse programming

Internal net drivers of a field programmable gate array are laid out with additional transistors to increase current drive capability at low supply voltages when a low supply voltage mask option is used. When a high supply voltage mask option is used, the additional transistors are not used in this way and the net drivers do not provide additional switching current drive capability. In some embodiments, were a low supply voltage mask option net driver operated at the high supply voltage, an impermissibly large switching current would flow through a programmed antifuse in a net coupled to the output of the net driver.

Three-statable net driver for antifuse field programmable gate array

A programmable integrated circuit (see FIG. 18) includes a plurality of interface cells with programmable antifuses disposed on a branch of a routing conductor. The routing conductor extends in a first direction and is coupled to one terminal of a programming transistor. The other terminal of the programming transistor is coupled to a programming driver via a programming conductor that extends in the first direction. The branch of the routing conductor crosses a plurality of routing wire segments of one of the interface cells, where programmable antifuses are disposed to couple the branch of the routing conductor to one or more of the routing wire segments. The routing wire segments extend parallel to one another in the first direction and are each coupled to a first terminal of separate programming transistors. The second terminals of the programming transistors are coupled to programming drivers via programming conductors that extend in a second direction, which is perpendicular to the first direction. Thus, the programming drivers for the routing wire segments and the routing conductor are positioned in different locations. Accordingly, when an antifuse is programming to couple the branch of the routing conductor with one of the routing wire segments, the two programming drivers are controlled by two different programming control shift registers.

Programmable integrated circuit having parallel routing conductors

A programmable integrated circuit (see FIG. 10) includes a routing conductor, i.e., 'express wire,' that extends substantially across the array of the integrated circuit. Because of the metal resistance through the long express wire, the express wire is simultaneously supplied with programming current from two different programming voltage terminals. Thus, programming current may be supplied to an electrode of an antifuse being programmed using programming current flowing through two separate programming voltage terminals. One programming voltage terminal supplies programming current via a first programming transistor and a first programming conductor to the express wire near one end of the programming conductor whereas another programming voltage terminal supplies programming current via a second programming transistor and a second programming conductor to the express wire near an opposite end of the express wire. The programming drivers that drive the first and second programming conductors are disposed adjacent opposite sides of the integrated circuit.

Programmable integrated circuit having a routing conductor that is

A programmable integrated circuit (see FIG. 9) has a plurality of L-shaped programming power buses (for example, 126, 130, 129 and 127) that extend along sides of the integrated circuit. Each L-shaped programming power bus extends along two adjacent sides of the integrated circuit such that legs of two L-shaped programming power buses extend along each of the sides. There are four pluralities of programming drivers (for example, 110, 117, 115 and 112), one plurality being associated with each of the four sides. There are also four programming current multiplexers (for example, 118, 125, 123 and 120), one associated with each of the sides. A programming driver of one of the plurality of programming drivers is selectively couplable to one of the two L-shaped programming power bus legs that extends along the associated side of the integrated circuit via the programming current multiplexer associated with that side. Additional pluralities of programming drivers and additional programming current multiplexers can be provided.

Programmable integrated circuit having L-shaped programming power buses

An interface cell for a programmable integrated circuit includes a pad, an input buffer, a first routing conductor, a plurality of second routing conductors, and a plurality of antifuses. The input of the input buffer is coupled to the pad and the output of the input buffer is coupled to the first routing conductor so that an input signal from the pad can be supplied onto the first routing conductor without passing through any programmed antifuses. The second routing conductors extend parallel to one another in a direction perpendicular to the direction in which the first routing conductor extends. The second routing conductors cross the first routing conductor and then pass out of the interface cell and into a routing channel of the programmable integrated circuit. One of the antifuses is disposed at each location where one of the second routing conductors crosses the first routing conductor. Accordingly, an input signal from the pad can be supplied onto any desired one of the second routing conductors of the routing channel by programming only one antifuse. The interface cell contains an enablable register, the control inputs of which can be independently driven from any conductor in the adjacent routing channel. Combinatorial and registered outputs of the interface cell can be simultaneously routed to the routing channel and some interface cell outputs have 2.times. drive strength.

Interface cell for a programmable integrated circuit employing antifuses

A programmable integrated circuit such as a field programmable gate array (see FIG. 3) has a few long routing wire segments for transmitting signals long distances across the integrated circuit. These long routing wire segments can be coupled together with programmed antifuses. A high-drive output driver may be used to drive signals a long distance through such coupled together long routing wire segments giving rise to large switching currents across the programmed antifuses that couple the long wire segments together. In some types of antifuses, programmed antifuse reliability is dependent upon maintaining the programming current used to program the antifuse a certain factor greater than the peak switching current flowing through the antifuse during normal operation. The antifuses in these long wire segments therefore should be programmed with proportionately larger programming currents. To increase the programming currents with which these antifuses are programmed, programming current is supplied onto each of the long routing segments from two different programming conductors via two different programming transistors.

Growing community of inventors

San Jose, CA, United States of America

Paige A Kolze