National Semiconductor Corporation

Pai-Hsiang Kao

Nikhil Vishwanath Kelkar

William Jeffrey Schaefer

Ranjan J Mathew

Cornelio De Vera

Disclosed is a packaged integrated circuit device. The device includes a die having a plurality of electrical contacts on a first surface of the die and a protective film adhered directly to a back surface of the die, the protective film being thick enough to allow laser marking of the protective film without the laser penetrating to the die. In one preferred embodiment, the protective film of the device is a thick film formed by screen printing. In a preferred embodiment, the protective film has a thickness of between about 1.5 and 5 mils. Also, disclosed is a method of fabricating a semiconductor wafer having a wafer substrate with a top surface and a bottom surface and a plurality of dies. In this embodiment, the method includes providing a plurality of dies on the top surface of the wafer substrate, applying a thick film over the bottom surface of the wafer substrate, adhering the thick film to a mounting tape that is not ultraviolet curable, and dicing the wafer to separate the dies. The thick film reduces chipping along edges of the separated dies.

Semiconductor wafer having a bottom surface protective coating

An improved integrated circuit device that includes both bond pads and trim pads is disclosed. Electrically conductive, non-wettable and non-corrosive protective caps are formed over each of the trim pads. With this arrangement, the protective caps act as barriers between the trim pads and solder used to form solder bumps when the IC package is mounted onto a substrate. In one embodiment, the protective caps are formed from a material that is easily sputtered, such as titanium. In a method aspect of the invention, the protective caps are applied during wafer level processing before either the solder bumping or trimming operations.

Metal pads for electrical probe testing on wafer with bump interconnects

A light shield is provided for light sensitive flip chip integrated circuits. The flip chip includes an under bump layer to portions of which solder bumps are attached. A separate portion of this under bump layer is used to provide the light shield. The light shield excludes ambient light from the most light sensitive portions of the circuit so that the electrical characteristics of the flip chip integrated circuit are not significantly altered when the flip chip is operated in ambient light.

Opaque metallization to cover flip chip die surface for light sensitive semiconductor devices

Disclosed is an IC package. The IC package includes a die having a plurality of conductive pads. A passivation layer is formed over the conductive pads such that the passivation layer has a plurality of passivation vias. Each passivation via is positioned over an associated one of the conductive pads. A resilient protective layer is formed over the passivation layer. The resilient protective layer has a plurality of resilient vias, wherein each resilient via is associated with an associated passivation via. A plurality of under bump pads are in electrical contact with the conductive pads, and each under bump pad is associated with one of the resilient vias. A plurality of contact bumps are formed over the plurality of under bump pads such that each one of the contact bumps is electrically coupled with a selected one of the under bump pads and such that each contact bump is electrically coupled with a selected one of the conductive pads. The resilient protective layer is arranged to absorb stresses introduced at the contact bumps when the IC package is attached to an external substrate; the contact bumps are formed from a material that facilitates absorption of stresses by the resilient protective layer, and the resilient protective layer is further arranged to protect the die. In one preferred embodiment, each under bump pad includes a lip that extends over a portion of the resilient layer. In another preferred embodiment, the contact bumps are formed from a eutectic tin-lead alloy. In another embodiment, a circuit board is disclosed. The circuit board includes a substrate having a plurality of board contacts and the IC package as recited above. In this embodiment, the IC package is attached to the substrate such that each of the contact bumps is coupled with an associated one of the board contacts. In a preferred embodiment, the resilient protective layer of the IC package absorbs stresses introduced at the contact bumps such that an underfill layer is not required between the IC package and the substrate.

Surface mount die: wafer level chip-scale package and process for making

Disclosed are methods and apparatuses that allow the dicing of wafers containing microelectromechanical systems into singulated individual dies that is economic to use and leaves substantially no residue on the surface of the individual dies. A method for packaging the dice singulated according to the present invention is also disclosed.

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Saratoga, CA, United States of America

Pai-Hsiang Kao