Monterey Design Systems, Inc.

Padmini Gopalakrishnan

Salil Ravindra Raje

Lawrence Thomas Pileggi

Dinesh D Gaitonde

Olivier R Coudert

Jackson David Kreiter

Methods and apparatus for a physical &ldquo;sign-off&rdquo; prototype tool that includes a prototype tool that generates a physical prototype for a design and a optimization tool that provides a designer with the option to further optimize the physical prototype before signing off on the design. In either situation, the &ldquo;sign-off&rdquo; prototype provides a forward prediction of the area, timing and performance of the final GDS of the design generated by a physical implementation tool.

Method and apparatus for generating sign-off prototypes for the design and fabrication of integrated circuits

Method to optimize net lists used in the design and fabrication of integrated circuits by using simultaneous placement optimization, logic function optimization and net buffering algorithms. Method simultaneously obtains a placement of logic functions, mapping of logic functions on to library elements and buffering of nets connecting the logic functions.

Growing community of inventors

Sunnyvale, CA, United States of America

Padmini Gopalakrishnan