Intel Corporation

Padmashree K Apparao

Zhen Zhou

Ravindra V Velhal

Thomas L Carr

Ravishankar Iyer

Robert F Kwasnick

Krishna Kant

Michal Karzynski

Various embodiments are generally directed to an apparatus, system, and other techniques for dynamic and intelligent deployment of a neural network or any inference model on a hardware executor or a combination of hardware executors. Computational costs for one or more operations involved in executing the neural network or inference model may be determined. Based on the computational costs, an optimal distribution of the computational workload involved in running the one or more operations among multiple hardware executors may be determined.

Using computational cost and instantaneous load analysis for intelligent deployment of neural networks on multiple hardware executors

Systems, apparatuses and methods may provide for compressed virtual memory (CVM) management using CVM arbitration. CVM arbitration may monitor CVM utilization, tune CVM and update CVM settings that may be enabled upon reboot of a system and/or apparatus. The CVM arbitration may improve memory management, thereby improving system performance and user experience.

Dynamic configuration of compressed virtual memory

Methods and apparatus such as a processor platform to manage a process under a memory constraint are disclosed herein. An example method includes detecting that a process is to transition from a foreground mode of operation to a background mode of operation. Without transitioning the process to the background mode of operation, a projected out of memory score is calculated. The projected out of memory score is compared to a score threshold, and the process is terminated when the projected out of memory score is greater than the score threshold. When the projected out of memory score is less than or equal to the score threshold, the process is allowed to transition to the background mode of operation. A priority adjustor may determine a projected adjustment value, for example by determining a default adjustment value, or by performing a lookup of an adjustment value currently associated with a second process operating in the background mode. The background mode of operation may be at least one of a visible application, a secondary server, a hidden application, a content provider, or an empty application. Freeing up memory in advance of a subsequent low memory check ensures that low memory conditions are avoided more promptly.

Using a projected out of memory score to selectively terminate a process without transitioning to a background mode

System and techniques for memory management are described herein. A request for an adjusted process-value for a process may be received. Here, the adjusted process-value may be used to compare resident processes to determine which resident process will be terminated in certain circumstances. In response to the request for the adjusted process-value, a launch-time weight for the process may be obtained. The launch-time weight may be combined with a process-value to create an adjusted process-value. The adjusted process-value may then be returned to the requestor.

Memory management

A method and apparatus for on-demand CPU licensing. An embodiment of a processor license system includes an agent to determine that a computer processing element in a computer system is faulty or unreliable. The system further includes an activation license manager. The activation license manager provides automatic activation of a spare computer processing element for the computer system upon a determination by the agent that the computer processing element is faulty or unreliable.

On-demand CPU licensing activation

A system may comprise a first processor core, a second processor core and a processor core assignor. The first processor core may include a first circuit to generate a first data and a second processor core may include a second circuit to generate a second data. The processor core assignor may assign a first thread to the first processor core or to the second processor core based on the first data, the second data, and an application reliability requirement.

Quantifying core reliability in a multi-core system

A system includes a multi-core processor including a first processor core and a second processor core, and a core manager. The core manager is to receive data during an execution of an application by the first processor core, the data indicating a potential fault associated with the first processor core, determine to disable the first processor core based on the data, and activate the second processor core to execute the application.

Method and apparatus for disabling a processor core based on a number of executions of an application exceeding a threshold

In one embodiment, the present invention includes a method of analyzing an extensible markup language (XML) file, generating structural information for the XML file, and incorporating the structural information into the XML file. The structural information may correspond to a hierarchy of the file and may further include size information corresponding to elements of the file. In such manner, the structural information may be transmitted with the XML file and used to aid a receiver of the file in parsing. Other embodiments are described and claimed.

Growing community of inventors

Portland, OR, United States of America

Padmashree K Apparao