Nxp Usa, Inc.

Freescale Semiconductor,inc.

Padmaraj Sanjeevarao

Jon Scott Choy

David W Chrudimsky

Karthik Ramanan

Jacob Williams

Anirban Roy

Richard Eguchi

Tahmina Akhter

Maurits Mario Nicolaas Storms

A memory includes read circuitry for reading values stored in memory cells. The read circuitry includes flipped voltage followers for providing bias voltages to nodes of current paths coupled to sense amplifiers during memory read operations.

Memory read circuitry with a flipped voltage follower

A memory includes a plurality of one-time programmable (OTP) memory cells, wherein each OTP memory cell includes a corresponding storage element capable of being in a permanently blown state or non-blown state. In the non-blown state, the corresponding storage element is capable of being in a low conductive state (LCS) or high conductive state (HCS). Control circuitry is configured to, in response to a received read request having a corresponding access address which selects a set of OTP memory cells, direct write circuitry to apply a voltage differential across the corresponding storage element of each selected OTP memory cell sufficient to set the corresponding storage element to a predetermined one of the LCS or HCS, and, after the write circuitry applies the voltage differential across the corresponding storage element, direct read circuitry to read the selected OTP memory cells to output read data stored in the selected OTP memory cells.

Memory with one-time programmable (OTP) cells and reading operations thereof

A memory includes memory cells having two select transistors per cell. Each of the two select transistors are coupled to two different word lines with each word line being controlled by a separate addressable word line driver circuit. In some embodiments, providing two different word lines from two different word line drivers may provide for a memory where the word lines can apply different voltages based on the memory operation being performed.

Memory with cells having multiple select transistors

A non-volatile memory includes virtual ground circuitry configured to generate a virtual ground voltage at a virtual ground node, a memory array of memory cells in which each memory cell includes a select transistor and a storage element and is coupled to a first column line of a plurality of first column lines; and a first decoder configured to select a set of first column lines for a memory write operation to a selected set of the memory cells. The non-volatile memory also includes write circuitry configured to receive a write value for storage into the selected set of memory cells, and a first column line multiplexer configured to, during the memory write operation, couple each selected first column line of the set of first column lines to the write circuitry, and couple each unselected first column line of the plurality of first column lines to the virtual ground node.

Non-volatile memory with virtual ground voltage provided to unselected column lines during memory write operation

As disclosed herein, a memory includes an array of resistive memory cells and a voltage regulator circuit that provides a regulated voltage based on a circuit with a replica resistive storage element. The regulated voltage is applied to a mux transistor of a multiplexer of a column decoder that is used to select a particular column line of a memory array from a set of column lines to provide the proper voltage to the memory cell during a write operation to the memory cell.

Non-volatile memory with multiplexer transistor regulator circuit

A memory includes a plurality of word line drivers with each driver controlling the voltage of a word line and the voltage of a select line during a memory operation. The driver operates to couple the select line to a first voltage setting terminal when the word line is asserted and couple the select line to a second voltage setting terminal when the word line is not asserted.

Memory with select line voltage control

A magnetoresistive random access memory (MRAM) array has a corresponding MRAM cell, including a Magnetic Tunnel Junction (MTJ), at an intersection of each row and column. A first row of the array is configured as a single one-time-programmable (OTP) row, wherein a first MRAM cell in a first column is connected to a second MRAM cell in a second column. A first MTJ of the first MRAM cell is connected to a first bit line of the first column, and a second MTJ of the second MRAM cell is not connected to a second bit line of the second column. During a write to the first MRAM cell, write circuitry is configured to connect the first and second bit lines and the corresponding source lines such that the select transistors in the first and second MRAM cells are connected in parallel to drive a write current through the first MTJ.

Magnetoresistive random access memory (MRAM) with OTP cells

Embodiments of a magnetoresistive random access memory (MRAM) diagnostic system are provided, which includes: preconditioning all bit cells in an MRAM cell array to a data value of one during a diagnostic mode, wherein the MRAM cell array is implemented in an active side of a semiconductor substrate; applying a first magnetic disturb field having a predetermined field strength to the MRAM cell array, subsequent to the preconditioning, wherein the first magnetic disturb field is generated by an antenna implemented in a number of layers of conductive and dielectric material over the active side of the semiconductor substrate; performing a first error correcting code (ECC) read operation to read the MRAM cell array, subsequent to the applying the first magnetic disturb field; and in response to detecting at least one uncorrectable read during the first ECC read operation, setting a fail state and exiting the diagnostic mode.

Magnetic disturb diagnostic system for MRAM

A memory system has a decoder circuit that includes a first driver circuit having an input coupled to receive a first pre-decode signal. The first driver circuit includes transistors wherein a first current electrode of a first transistor is coupled to receive a second pre-decode signal. The decoder circuit includes a second driver circuit having an input coupled to receive a third pre-decode signal. The second driver circuit includes transistors wherein a first current electrode of a third transistor in the stack is coupled to receive the second pre-decode signal. A fifth transistor has a first current electrode coupled to an output of the first driver circuit, a second current electrode coupled to an output of the second driver circuit, and a control electrode coupled to a fourth pre-decode signal.

Decoder

A word line driver that includes a pull up transistor for biasing a node of a stack of transistors that are located between a high supply voltage terminal and a low supply voltage terminal. The node is biased at a voltage that is between the high supply voltage and the low supply voltage. The stack of transistors includes a stack of decode transistors and a cascode transistor. The cascode transistor is located between the node and a second node of the stack that is coupled to an inverting circuit.

Non-volatile memory (NVM) with word line driver/decoder using a charge pump voltage

A memory device includes a word line driver circuit, a write voltage generator for providing a write voltage to the word line driver during a write operation to memory cells coupled to the word line driver circuit, and a write bias generator including an output node for providing a write bias voltage that is different from the write voltage to the word line driver circuit during a write operation to memory cells coupled to the word line driver circuit. The write bias voltage is used to reduce current drawn by the word line driver circuit from the write voltage generator during a write operation to memory cells coupled to the word line driver circuit.

Flash memory with bias voltage for word line/row driver

A memory module decodes an address to determine a one or more wordline select pattern, or other spatial select pattern. An encoder determines an encoded value based upon the wordline select pattern that is compared to an expected encode value. The encode value has fewer than twice the number of address bits used to determine the wordline select pattern.

Memory device and method using encode values for access error condition detection

A first logic state is at a first output voltage level at a first output of a level shifter that selects a first negative regulation voltage level in response to the first logic state. A negative supply voltage begins at first potential and decreases to the first negative regulation voltage level. The first output voltage level decreases as the negative supply voltage decreases. The first output of the level shifter is switched from the first logic state to a second logic state in response to the negative supply voltage reaching the first negative regulation voltage level. The second logic state is provided at a second output voltage level that selects a second negative regulation voltage level for the negative regulation voltage. The first output of the level shifter remains at the second logic state but is reduced in voltage.

Negative voltage generation

A memory including a data line, a sense amplifier, and an array of memory cells. The memory includes a transistor for coupling the data line to memory cells of the array for reading. The transistor is biased at a voltage that is higher than a voltage that the data line is biased during precharging. The transistor is part of a regulation circuit. The regulation circuit includes transistors with a higher dielectric breakdown voltage than transistors of the sense amplifier.

Memory with high speed sensing

A memory has first and second memory arrays and first and second sense amplifiers coupled to the first and second memory arrays, respectively. A verify data line is coupled to first outputs of the first sense amplifier and the second sense amplifier as well as to a program/erase controller. The verify data line has a first logic circuit having a first input coupled to the first output of the first sense amplifier and an output. A second logic circuit has a first input coupled to the output of the first logic circuit, a second input coupled to the first output of the second sense amplifier, and an output. A global data line is coupled to a second output of the first sense amplifier and a second output of the second sense amplifier. A global sense amplifier is coupled to the global data line.

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Austin, TX, United States of America

Padmaraj Sanjeevarao