Broadcom Corporation

Padmanava Sen

Henrik Tholstrup Jensen

Stephen Wu

Georgios Sfikas

Emmanouil Frantzeskakis

Ioannis Loukas Syllaios

The present disclosure is directed to digital phase-locked loops (DPLLs) and hybrid phase-locked loops (HPLL) for establishing and maintaining a phase relationship between a generated output signal and a reference input signal. The DPLLs use a counter based loop to initially bring the DPLL into lock. Thereafter, the DPLLs disable the counter based loop and switch to a loop with a multi-modulus divider (MMD). The DPLLs can implement a cancellation technique to reduce phase noise introduced by the MMD. The HPLLs further include a loop with a MMD. The HPLLs can implement a similar cancellation technique to reduce phase noise introduced by the MMD.

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Irvine, CA, United States of America

Padmanava Sen