Hewlett-packard Company

Hewlett-packard Development Company, L.P.

Advanced Micro Devices Corporation

Hewlett-packard Development, L.p.

Padmanabha I Venkitakrishnan

Gopalakrishnan Janakiraman

Rajendra Kumar

Stuart Siu

Shankar Venkataraman

Tsen-Gong Jim Hsu

Paul S Keltcher

Joseph Ku

Stephen Richardson

Ronald C Laugesen

Gary Vondran

In one embodiment, for an electronic architecture with a functional constitution performing a number of functions characterized by separate stages performing subfunctions, a method of deriving a benchmark program for estimating the maximum power consumption by modeling a functional model of the architecture, compiling the benchmark program into a corresponding instruction stream, valuating power weights for each stage of each function of each constituent, inserting the power weights, running the model in a maximum power consumption mode, and summarizing power consumption. In one embodiment, the benchmark program is applied by specifying a design analysis to be performed, selecting a function, designating a stages performing that function, removing a set of instruction set architecture instructions corresponding the designated stage, emulating the constituent subfunction corresponding to the stages designated stage, and summarizing. In one embodiment, the model is written in SystemC. In one embodiment, a compiler used is a PERL script.

Method for deriving the benchmark program for estimating the maximum power consumed in a microprocessor

A streamlined cache coherency protocol system and method for a multiple processor single chip device. There are three primary memory unit (e.g., a cache line) states (modified, shared, and invalid) and three intermediate memory unit pending states. The pending states are used by the present invention to prevent race conditions that may develop during the completion of a transaction. The pending states 'lock out' the memory unit (e.g., prevent access by other agents to a cache line) whose state is in transition between two primary states, thus ensuring coherency protocol correctness. Transitions between states are governed by a series of request and reply or acknowledgment messages. The memory unit is placed in a pending state while appropriate measures are taken to ensure access takes place at an appropriate time. For example, a modification occurs only when other agents can not access the particular memory unit (e.g., a cache line).

Streamlined cache coherency protocol system and method for a multiple processor single chip device

Multiple processors are mounted on a single die. The die is connected to a memory storing multiple operating systems or images of multiple operating systems. Each of the processors or a group of one or more of the processors is operable to execute a distinct one of the multiple operating systems. Therefore, resources for a single operating system may be dedicated to one processor or a group of processors. Consequently, a large number of processors mounted on a single die can operate efficiently.

Chip multiprocessor with multiple operating systems

The present invention provides a new crossbar switch which is implemented by a plurality of parallel chips. Each chip is completely programmable to couple to every node in the system, e.g., from one node to about one thousand nodes (corresponding to present-day technology limits of about one thousand I/O pins) although conventional systems typically support no more than 32 nodes. The crossbar switch can be implemented to support only one node, then one chip can be used to route all 64 bits in parallel for 64 bit microprocessors.

Scalable, re-configurable crossbar switch architecture for multi-processor system interconnection networks

In one embodiment, the present invention provides a method for estimating the maximum power consumed in a microprocessor or other architecture, at an architectural level, prior to implementation. A functional model represents the architecture at a high level of abstraction. In one embodiment, the model is written in SystemC. In one embodiment, power consumption is expressed power weights, derived by reference to architecture technology. In one embodiment, a method of estimating power consumption prior to implementation operates by modeling a benchmark, compiling it into an instruction stream, assigning power weights for each stage of each architectural function, running the model in a maximum power consumption mode, and summarizing the resulting power consumption. In one embodiment, a PERL script compiler is used. In one embodiment, the power weights are calculated corresponding to the characteristic architecture technology. In one embodiment, a power virus program runs the model in the maximum power mode.

Method for estimating the power consumed in a microprocessor

A distributed shared memory multi-processor system includes a System Control Unit (SCU) which is made up of a system control unit address section (SCUA) and system control unit data sections (SCUDs). The SCU is scalable by dividing the control and data flow functions of the SCU, and then parallelizing the data path. This allows the number of processors in the system to be increased or higher performance processors to be added by increasing the number of SCUDs and reprogramming crossbar switches incorporated in the SCUA and SCUDs. This results in the overall increase of the multi-processor system performance.

Scalable system control unit for distributed shared memory multi-processor systems

A network of integrated communication switches and coherence controllers is provided which interconnected nodes in a cache-coherent multi-processor computer architecture. The nodes contain multiple processors operatively connected to associated memory units through memory controllers. The communication switches and coherence controllers has associated coherence directories which maintain coherence information for all memory lines that are &ldquo;homed&rdquo; in the nodes that are directly connected to the particular communication switch and coherence controller.

Distributed directory cache coherence multi-processor computer architecture

The present invention provides a new crossbar switch which is implemented by a first plurality of chips. Each chip is completely programmable to couple to every node in the system, e.g., from one node to about one thousand nodes (corresponding to present-day technology limits of about one thousand I/O pins) although conventional systems typically support no more than 32 nodes. The crossbar switch can be implemented to support only one node, then one chip can be used to route all 64 bits in parallel for 64 bit microprocessors. A second plurality of chips in parallel provides the redundancy necessary for a high availability system.

Backup redundant routing system crossbar switch architecture for multi-processor system interconnection networks

A monolithic integrated circuit chip preferably includes a pair of data busses capable of conducting in parallel the number of signals which can be processed simultaneously by the components on the chip. Signals on the busses are carried in a time-multiplexed manner, each bus having a predetermined number of time slots. Preferably, each component on the chip is connected to one or both of the busses and is assigned a particular time slot for the bus to which it is connected. The resulting chip is of a structured, rather than a custom, design. Accordingly, it can be readily expanded or contracted in the number of signals which can be simultaneously processed. The number of components which can be included on the chip is limited only by the number of time slots available on the bus to which it is connected. By providing two busses, such common circuit elements as two-input adder/subtractors can be readily accommodated by a chip designed according to the instant invention. The bit-slice organization of the chip significantly reduces the design effort of the components connected to a bus, since a one-bit slice is merely replicated for each conductor of the bus. Ease of expansion along this dimension is achieved at virtually no cost.

Growing community of inventors

Sunnyvale, CA, United States of America

Padmanabha I Venkitakrishnan