Quantum Corporation

Hgst Technologies Santa Ana, Inc.

International Business Machines Corporation

Microsoft Technology Licensing, LLC

S-tec Corporation

Western Digital Technologies, Inc.

Hgst Netherlands, B.v.

Pablo A Ziperovich

Aldo Giovanni Cometti

Richard Leo Galbraith

Jonathan Darrel Coker

Kevin Dean Fisher

Anthony Dwayne Weathers

Majid Anaraki Nemati

Xiaodong Che

Bruce Douglas Buch

Mark Moshayedi

Wolfgang H Schott

Francois Bernard Dolivo

Ashot Melik-Martirosian

James Chiao

Thomas Lau

This disclosure describes systems and methods for detecting multiple insertion and deletion errors in the presence of substitution errors in a signal (such as a sequenced DNA string). A convolutional code that includes two or more component convolutional codes is used for encoding. Each of the two or more component convolutional codes generates only a subset of all possible outputs of the convolutional code. The subsets of the two or more component convolutional codes are disjoint from each other. Only one of the two or more convolutional codes is active at any given time. The two or more convolutional codes together define a super code. The two or more convolutional codes are time interlaced within the super code, and the super code defines the convolutional code. A trellis that includes two or more component trellises designed based on the two or more component convolutional codes is used for decoding.

Codes to detect insertion and deletion errors in a dense storage medium

A method for data retrieval includes receiving a set of probability metrics. A set of probability metrics is received for each one of a plurality of read values, and each probability metric of the set of probability metrics corresponds to a statistical likelihood that the read value is representative of one of a number of symbols. The symbols define a set of allowed transitions between a number of states, and a series of successive allowed transitions between states define allowed paths between the states. The method further includes determining a survival path between the states. The survival path is based on an accumulation of probability metrics corresponding to the statistical likelihood that successive ones of the plurality of read values are representative of successive ones of the symbols defining each transition in the survival path. The method further includes decoding a symbol stream based on the survival path.

Systems and methods for encoding and decoding data

A flash memory controller is configured to provide a first erase mode for erasing one or more groups of flash memory cells in a flash memory device using a plurality of erase pulses and a second erase mode for erasing the one or more groups of flash memory cells using a single erase pulse. The controller may receive a fast erase signal to erase the one or more groups of flash memory cells and, in response to the signal, switch operating parameters of the flash memory device from first parameters corresponding to the first erase mode to second parameters corresponding to the second erase mode, and instruct the flash memory device to perform an erase operation on the one or more groups of flash memory cells according to the second parameters. The controller may then verify that the erase operation was completed using the single erase pulse.

Fast secure erase in a flash system

Disclosed is an apparatus and method for determining memory cell bias information for use in memory operations. One or more memory die are selected from a group of memory die, and one or more memory blocks selected from the selected one or more memory die. A group of cells within the selected memory blocks are programmed and cycled. Bias values are generated based on comparing one or more program levels associated with respective wordlines with predetermined programming levels. The bias values are stored lookup table that is configured to be accessible at runtime by a memory controller for retrieval of the bias value during a memory operation.

Determining bias information for offsetting operating variations in memory cells

Disclosed is an apparatus and method for adjusting operating parameters in a storage device. A controller in a solid state drive monitors current operating conditions of the drive's flash memory, and when the flash memory has been subjected to a predetermined number of program/erase cycles one or more stored bias values are retrieved from a storage location based on the wordline(s) associated with a current memory operation. Parameters of the memory operation are then adjusted based on the retrieved bias values, and the memory operation is performed using the adjusted parameters.

Setting operating parameters for memory cells based on wordline address and cycle information

Disclosed is an apparatus and method for providing memory cell bias information for use in memory operations. One or more memory die are selected from a group of memory die, and one or more memory blocks selected from the selected one or more memory die. A group of cells are programmed within the selected memory blocks, and one or more distributions of cell program levels associated with a group of wordlines are determined. A bias value for each wordline is then generated based on comparing one or more program levels in a distribution of program levels associated with the respective wordline with predetermined programming levels. The bias values are stored lookup table that is configured to be accessible at runtime by a memory controller for retrieval of the bias value during a program or read operation.

Determining bias information for offsetting operating variations in memory cells based on wordline address

Disclosed is an apparatus and method for adjusting operating parameters in a storage device. A controller in a solid state drive monitors current operating conditions for blocks of memory used to store data in the drive. When a block has been subjected to a predetermined number of program/erase cycles one or more stored bias values are retrieved from a storage location based on the wordline(s) associated with a current memory operation. The one or more parameters of the memory operation are then adjusted based on the one or more stored bias values, and the memory operation performed on the block of memory cells using the adjusted parameters.

Adjusting operating parameters for memory cells based on wordline address and cycle information

A method for suspending an erase operation performed on a group of memory cells in a flash memory circuit is disclosed. One example method includes providing to the memory circuit a command to erase the group of memory cells via a plurality of erase pulses. After applying an erase pulse, if it is determined that another operation has a priority higher than a predetermined threshold, the method suspends the erase operation, performs the other operation, and then resumes the erase operation.

Erase-suspend system and method

A power-reduced digital control within a feedback control loop of a sampling data detection channel controls a predetermined operating parameter of the channel in which an analog to digital converter provides digital samples of information in the channel at a predetermined channel clock rate. The digital control comprises a parameter error extraction circuit clocked at the predetermined channel rate which is connected to receive digital samples from the analog to digital converter, and which extracts parameter error values from the digital samples; an averaging circuit for averaging the extracted parameter error values over an integral submultiple of the predetermined channel clock rate; and a parameter error processing circuit which is connected to the parameter error extraction circuit and clocked at the integral submultiple of the predetermined channel rate for generating and putting out digital control values within the feedback control loop for controlling the predetermined operating parameter. The parameter may be timing, gain or DC offset, and the sampling data detection channel may be a PRML channel of a magnetic hard disk drive. A power-reduced control method is also described.

Control loops for low power, high speed PRML sampling data detection

A modulation method generates a rate 16/17 (d=0, G=7/I=11) modulation code for transferring user digital data bytes having a three-way ECC interleave through a data transfer channel in accordance with the steps of:

Bit-interleaved rate 16/17 modulation code with three-way

An on-chip self-test circuit for testing digital elements of a synchronous sampling data detection channel chip, such as a PRML channel of a hard disk drive, with digital pseudo samples representative of samples coming from an analog channel section, includes a sample generator generating idealized digital pseudo samples in accordance with a predetermined spectrum response, a digital noise generator generating digital noise values, a first combining circuit combining the idealized digital pseudo samples with the digital noise values to produce noisy pseudo samples, a bias injection circuit connected to the sample generator and adding a predetermined bias to the idealized digital pseudo samples to produce biased pseudo samples, and a second combining circuit for combining the noisy pseudo samples with the biased pseudo samples to put out biased noisy pseudo samples to test digital data processing and channel control elements of the channel chip.

Method for in-chip testing of digital circuits of a synchronously

A new method for overlapping block read events in a disk drive having synchronously sampled data detection channels is presented. In particular, the new method is for overlapping read back processing by real-time and digital signal processing of first and second data blocks from a storage medium. The method includes steps of clocking real-time and digital signal processes by a clock synchronized to the first data block while the first data block is passing by a data transducer head, clocking the digital signal processes for the first data block by an asynchronous clock operating at a nominal data clocking rate after the first data block has passed by the data transducer head and before a clock has synchronized to the second data block following the first data block, and clocking real-time signal processes for the second data block and completing clocking of the digital processes for the first data block by a clock synchronized to the second data block passing by the data transducer head. The storage medium can be a magnetic hard disk, magnetic tape, or an optical disk, for example.

Method for overlapping block read events in disk drive

Write precomposition optimization for a partial response maximum likelihood ('PRME') magnetic recording chapel adapted to a mass production environment. Optimal write precompensation may be determined by writing a tribit data pattern known to produce worst case nonlinear transition shift ('NLTS') onto a magnetic recording medium; reading back the recorded data pattern; and calculating the mean-squared error ('MSE') for one or more of the equalized data sample levels associated with the PRML channel to be optimized. The writing and reading back process is repeated with varying amounts of precompensation applied to the written pattern. The optimal amount of write precompensation is determined eider by minimizing the MSE for a selected sample level or by minimizing MSE between the middle and the upper or lower of the ternary PRML sample levels.

Growing community of inventors

San Jose, CA, United States of America

Pablo A Ziperovich