New York University

University of Texas System

Ozgur Sinanoglu

Jeyavijayan Rajendran

Ramesh Karri

Youngok Pino

Muhammad Yasin

Vinayaka Jyothi

Jeyavijayan Rajendra

Exemplary system, method, and computer-accessible medium for protecting at least one logic-locked integrated circuit (IC) design can include, for example, receiving a request(s), and swapping a correct key which is configured to unlock the logic-locked IC design(s) with an incorrect key which is configured to corrupt an output(s) of the logic-locked IC design(s) after receipt of the request(s). The request(s) can be a test access request(s). The correct key can be utilized when the logic-locked IC design(s) can be initially powered on. The correct key can be swapped with the incorrect key using multiplexer(s) or register(s). In addition, exemplary system, method, and computer-accessible medium can be provided for logic-locking a logic design by, randomly replacing randomly-selected inverters in the logic design with XOR or XNOR key-gates, and inserting XOR or XNOR key-gates randomly in randomly-selected locations in the logic design where there is no inverter.

System, method, computer-accessible medium, and circuit for crippling the oracle in logic locking

An exemplary system, method and computer-accessible medium for modifying a design of an integrated circuit(s) (ICs), which can include, for example, modifying a logic gate(s) in the design for a protected input pattern(s), and providing a restoration unit(s) into the design, where the restoration unit(s) can be configured to (i) produce an error-free output(s) when a correct secret key can be applied to the restoration unit(s), and (ii) produce an erroneous output(s) when an incorrect key can be applied to the restoration unit(s); and ensure that the modified design along with the restoration unit produces at least one erroneous output with respect to the original design for only a pre-determined constant number of incorrect keys based on at least one input pattern.

System, method and computer-accessible medium for stripped-functionality logic locking

Exemplary embodiment of the present disclosure can include, for example, a logic-locking circuit ('SARLock'), which can include a logic cone(s) receiving a distinguishing input pattern(s) (DIP), a comparator(s) receiving the DIP(s) and a key value(s), and a logic gate(s) connected to an output of the logic cone and to an output of the comparator. A mask(s) can be connected to the comparator(s) and the logic gate(s). The logic gate(s) can be a XOR gate(s). The comparator(s) can be configured to flip a signal(s) based on a combination of the DIP(s) and the key value(s). A mask(s) can be connected to the comparator(s) and the logic gate(s), which can be configured to prevent the flipped signal(s) from being asserted for a correct key value(s).

System, method and computer-accessible medium for satisfiability attack resistant logic locking

Exemplary embodiments of the present disclosure can include an exemplary system, method and computer-accessible medium for camouflaging a design of an integrated circuit(s) (IC), can include, for example, receiving information related to a plurality of input combinations to the ICs, and camouflaging the design of the ICs by limiting a discriminating ability of the input combination to a predetermined constant number of incorrect assignments. An incorrect output can be intentionally produced for a predetermined constant number of secret minterms of the ICs. An output of the ICs can be restored for the secret minterms using a CamoFix block. The CamoFix block can include a CamoInputMapping block(s), a CamoSecGen block(s) or a comparator block(s).

System, method and computer-accessible medium providing secure integrated circuit camouflaging for minterm protection

An exemplary system, method and computer-accessible medium can be provided which can include, for example, generating a super control dataflow graph(s) (CDFG) by applying a plurality of electronic system level ESL design constraints associated with an integrated circuit, determining an upper bound(s) number and a lower bound(s) number based on a number of CDFGs in the super CDFG(s)&#x2014;with each number being one metric of a capability of the integrated circuit to resist reverse engineering attack&#x2014;, and inserting a component(s) into a register transfer level netlist to effectuate a modification of the upper bound(s) and the lower bound(s).

System, method and computer-accessible medium for security-centric electronic system design

Exemplary systems, methods and computer-accessible mediums can secure split manufacturing of an integrated circuit by modifying a previous location of at least one pin to a further location of the at least one pin based on a fault analysis procedure. A determination of the further location can include an iterative procedure that can be a greedy iterative procedure. The modification of the location of the at least one partition pin can be performed by swapping at least one further partition pin with the at least one partition pin.

System, method and computer-accessible medium for providing secure split manufacturing

Exemplary systems, methods and computer-readable mediums can assign, from the circuit, at least two scan cells as at least two interface registers, and generate at least one bidirectional scan path between the at least two interface registers of the at least one portion of the circuit. The at least two interface registers can be disposed in neighboring positions, and the assigning can include a partitioning procedure that can iteratively merge the scan cells of the at least one portion of the circuit into a plurality of regions.

Systems, processes and computer-accessible medium for providing a bi-directional scan path for peak capture power reduction in launch-off-shift testing

Exemplary systems, methods and computer-accessible mediums can encrypting a circuit by determining at least one location to insert at least one gate in the circuit using a fault analysis, and inserting the at least one gate in at least one section of the at least one location. The determination can include an iterative procedure that can be a greedy iterative procedure. The determination can be based on an effect of the particular location on a maximum number of outputs of the circuit.

Systems, processes and computer-accessible medium for providing logic encryption utilizing fault analysis

Exemplary method, computer-accessible medium, and test configuration can be provided for testing at least one flip-flop. For example, the exemplary test configuration can include at least one scan-out channel having a plurality of regions and a plurality of compactors associated with the plurality of regions. Further, exemplary method, computer-accessible medium, and test configuration can be provided for testing at least on flip-flop that in which at least one scan-out channel having a plurality of regions, a plurality of compactors, and associating the plurality of compactors with the plurality of regions can be provided.

Architecture, system, method, and computer-accessible medium for expedited-compaction for scan power reduction

Exemplary systems, methods and computer-accessible mediums can be provided that can, for example, determine a camouflaging location(s) of the logic gate(s) using a fault analysis procedure, and can camouflage the logic gate(s) at the location(s) based on the determination. The camouflaging procedure can be performed by replacing the logic gate(s) at the camouflaging location(s) with a further camouflaged gate, which can have a dummy contact(s) or a vias.

System, method and computer-accessible medium for fault analysis driven selection of logic gates to be camouflaged

Exemplary systems, methods and computer-accessible mediums for encrypting at least one integrated circuit (IC) can include determining, using an interference graph, at least one location for a proposed insertion of at least one gate in or at the at least one IC, and inserting the gate(s) into the IC(s) at the location(s). The interference graph can be constructed based at least in part on an effect of the location(s) on at least one further location of the IC(s).

System, method and computer-accessible medium for facilitating logic encryption

Exemplary method, computer-accessible medium, test architecture, and system can be provided for a partial-scan test of at least one integrated circuit. For example, it is possible to obtain a plurality of test cubes using a first combinational automatic test pattern generation (ATPG) and identify at least one flip-flop of the integrated circuit using the test cubes to convert to a non-scan flip-flop and facilitate the partial-scan test to utilize the cubes without a utilization of a sequential ATPG or a second combinational ATPG.

Architecture, system, method, and computer-accessible medium for partial-scan testing

Exemplary system, method and computer-accessible medium for testing a multi-core chip can be provided which can have and/or utilize a plurality of identical cores. This can be performed by comparing each core with as many as at least the number of spare cores plus 1 using a comparator; the number of comparators can equal the total number of cores multiplied by one-half the number of spare cores plus 1. A mismatch between two cores can identify at least one of the two cores as defective and a perfect match between two cores can identify both cores as not defective. The multi-core chip can fail the test if the number of defective cores can be greater than the number of spare cores.

Test access system, method and computer-accessible medium for chips with spare identical cores

Exemplary system, method and computer accessible medium that can transform a circuit by selecting at least one scan cell as an interface register and inserting a shadow register into each interface register. Operations can be shifted to load and unload at least one scan cell in the circuit. An operation can be launched in at least one of the interface registers and in a first set of scan cells. A capture operation can be performed in a second set of scan cells. An operation can be restored in at least one interface register by transferring data from at least one shadow register.

System, method and computer-accessible medium for design for testability support for launch and capture of power reduction in launch-off-capture testing

A ring oscillator (RO) based Design-For-Trust (DFTr) technique is described. Functional paths of integrated circuit (IC) are included in one or more embedded ROs by (1) selecting a path in the IC, based on path selection criteria, that has one or more unsecured gates, and (2) embedding one or more ROs on the IC until a stop condition is met. An input pattern to activate embedded RO is determined. Further, a golden frequency which is a frequency at which the embedded RO oscillates, and a frequency range of the embedded RO are determined. A Trojan in the IC may be detected by activating the embedded RO (by applying the input pattern), measuring a frequency at which the embedded RO oscillates, and determining whether or not a Trojan is present based on whether or not the measured frequency of the RO is within a predetermined operating frequency range of the RO.

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Abu Dhabi, United Arab Emirates

Ozgur Sinanoglu