Mellanox Technologies, Ltd.

Oz Harel

Hananel Faig

Yair Yakoby

A receiver including an equalization component to receive a signal comprising a sequence of samples corresponding to symbols and generate an equalized signal with an estimated sequence of symbols corresponding to the signal. The receiver further includes a decision generation component to detect that an aggregate error level associated with the equalized signal exceeds a saturation threshold level. The decision generation component identifies a set of errors including a first error associated with a first symbol having a highest error level and a last error associated with a last symbol. The decision generation component generates, based on the equalized signal, a decision including a sequence of one or more bits that represent each symbol of a first subset of the sequence of symbols and a confidence level corresponding to the decision, where the confidence level is based at least in part on a distance between an error level of each symbol and a level of the first error.

Digital signal symbol decision generation with corresponding Forney-based confidence level

A receiver includes an analog-to-digital converter (ADC) to generate a digital output, including a set of bits corresponding to a received signal. The receiver further includes a calculator circuit coupled to the ADC, the calculator circuit to calculate a set of tap coefficient gradient values corresponding to the digital output, generate a first feedback signal corresponding to the set of tap coefficient gradient values, and generate a second feedback signal corresponding to the set of tap coefficient gradient values. The receiver further includes a clock data recovery (CDR) circuit, coupled to the calculator circuit, the CDR circuit to detect a first parameter of the received signal based on the first feedback signal. The receiver further includes a feed forward equalization (FFE) system, coupled to the calculator circuit, the FFE system including multiple filter taps having a set of filter tap coefficients to be adapted based on the second feedback signal to generate a set of adapted filter tap coefficients.

Clock and data recovery circuit and feed forward equalizer decoupling

A receiver including an equalization component to receive a signal comprising a sequence of samples corresponding to symbols and generate an equalized signal with an estimated sequence of symbols corresponding to the signal. The receiver further includes a decision generation component to receive the equalized signal and generate, based on the equalized signal, a decision comprising a sequence of one or more bits that represent each symbol of the sequence of symbols and a confidence level corresponding to the decision.

Growing community of inventors

Ness Ziona, Israel

Oz Harel