International Business Machines Corporation

Oz Dov Hershkovitz

Avishai Moshe Fedida

Michal Rimon

Olaf Knute Hendrickson

Silvia Melitta Mueller

Christopher A Krygowski

Gal Ashour

Eyal Naor

Erez Barak

Yoav Avraham Katz

Karen Holtz

Ofer Peled

Eli Almog

Gilad Merran

Ofek Gutman

Adi Dagan

Craig T Atherton

Embodiments of the present disclosure are directed to an efficient and uniform process for generating multiple outputs for different generated test cases for an input request that share a common section in a pseudo-random software system. An enhanced disclosed method comprises processing an input request and a sequence of instructions until a state or condition of interest is reached in a first process. The condition of interest is marked as a split point in the first process. At the split point, a next process for generating multiple outputs is created to include a common section of the first process from the input request to the split point, an added form of randomization, and at least one instruction after the split point. The common section is generated only once in the first process, which can provide significantly enhanced performance.

Uniform process for generating multiple outputs with common section in pseudo-random software system

A method of salvaging an output is provided. The method includes defining a condition for terminating a run of a tool, checking whether the condition is likely to be met during a running of the tool, terminating the running in an event the condition is likely to be met, checking a validity of an incomplete output of the tool generated during the running and finalizing the incomplete output in an event the incomplete output is valid.

Salvaging outputs of tools

An approach to create a multiple use test case when one or more computer processors receive a first test case from a test generator. The approach includes the computer processors evaluating each instruction in the first test case to determine that an instruction meets a set of conditions for creating a multiple use test case. The method includes one or more computer processors generating a set of rules for each instruction meeting the one or more conditions to create the multiple use test case. Furthermore, the method includes one or more computer processors creating the multiple use test case by adding the set of rules to each instruction meeting the one or more conditions to create the multiple use test case.

Creating multiple use test case

Validating microprocessor instruction execution by receiving a floating-point exception selection, receiving a validation method selection, generating validation data according to the floating-point exception selection and the validation method selection by randomly generating a first tensor element value and randomly generating a second tensor element value according to the first tensor element value and the floating-point exception selection, and executing a floating-point computation according to the validation data.

Validating microprocessor performance

A method for flexible test program generation is described that alters previously used resources. The method includes scanning, by a test generator, a set of instructions that have been executed by a system under test (SUT) using a reference model of the SUT. The method further includes identifying, by the test generator, a resource for using in a test program by determining an allocation of a first value to the resource by a subset of instructions from the set of instructions, wherein the first value of the resource is not used after the allocation. The method further includes modifying the subset of instructions to allocate a second value to the resource, and adding to the set of instructions, at least one instruction that uses the second value to perform a predetermined operation. The SUT is tested based on a result of the predetermined operation that uses the second value.

Flexible test program generation by altering previously used resources

Error checking for a computer processor design under test. In multiple processing threads, and in accordance with a hardware model of a computer processor design under test, the instructions of multiple instruction sequences corresponding to the processing threads are processed, thereby resulting in an order in which the instructions are processed in accordance with the hardware model, and producing an actual result for each of the instructions. An expected result is determined for any of the instructions in accordance with a reference model of the computer processor design under test and in accordance with the order in which the instructions were processed in accordance with the hardware model. Any of the instructions whose expected result and actual result differ are identified.

Error checking of a multi-threaded computer processor design under test

A method and apparatus are provided for implementing random content of program loops in random test generation for processor verification. A converged branch instruction stream is used by a test generator to ensure that all random conditional branches converge to a main program loop. A built in exception handling mechanism of the test generator enables program interrupts to converge to the main program loop. Mandatory read only registers applied to the test generator allow all register based storage addresses to use registers that maintain a value and thus stabilize the storage address translations through subsequent iterations of the loop. A global class restriction mechanism defines specific restricted instruction classes applied to the test generator avoids inherently problematic operations for the program loops. Machine state detection and restoration mechanisms in the test generator are provided to preserve storage addressability.

Implementing random content of program loops in random test generation for processor verification

A method and apparatus are provided for implementing automated memory address recording in constrained random test generation for verification of processor hardware designs. A test generation program includes a built in feature to keep track of storage addresses used and to make the addresses available to the test definition. This built in feature of a constrained random test generator allows storage addresses used in the past to be accessed by the current instruction generation eliminating the requirement of deliberately establishing target addresses first. This allows separate test events to interact with the same storage addresses without having to write a special test.

Implementing automated memory address recording in constrained random test generation for verification of processor hardware designs

A computerized apparatus, method and computer product for generating tests. The apparatus comprises: a processor; an interface for obtaining a test template associated with a computerized system that comprises a template segment comprising instructions and directives or related control constructs; a test generator for generating a test associated with the template segment, comprising: a simulator for determining a state of the system associated with an execution of the test; a selector for selecting a template instruction or segment from the test template based on the state of the system; and a generator configured to generate a multiplicity of instructions based on system's state and on the selected template segment, wherein the test generator further comprises a verifier configured to verify that a previously generated instruction is in line with the current state of the system and with the selected template instruction or segment.

Dynamic generation of test segments

Verification of a system-under-test (SUT) supporting the functionality of operating a self modifying code is disclosed. A generator may generate a self modifying code. In response to identification that a simulator is about to simulate code generated by the self modifying code, the simulator may simulate the execution in a 'rollover mode'. The code may include instruction codes having variable byte size, branching instructions, loops or the like. The simulator may further simulate execution of an invalid instruction. The simulator may perform rollback the simulation of the rollover mode in certain cases and avoid entering the rollover mode. The simulator may perform rollback in response to identifying a termination condition, as to insure avoiding endless loops. The simulator may perform rollback in response to reading an initialized value that is indefinite.

Growing community of inventors

Zichron Yaacov, Israel

Oz Dov Hershkovitz