International Business Machines Corporation

Owen Chiang

Dung Q Nguyen

Peter Juergen Klim

Christopher McCall Durham

David R Terry

Steven J Battle

Saiful Islam

Sam G Chu

Eula A Tolentino

James Douglas Warnock

Robert N Krentler

Albert James Van Norstrand, Jr

Daniel Lawrence Stasiak

Douglas Hooker Bradley

Sherman Matthew Dance

Reducing power consumption in a multi-slice computer processor that includes a re-order buffer and an architected register file, including: designating an entry in the re-order buffer as being invalid and unwritten; assigning a pending instruction to the entry in the re-order buffer; responsive to assigning the pending instruction to the entry in the re-order buffer, designating the entry as being valid; writing data generated by executing the pending instruction into the re-order buffer; and responsive to writing data generated by executing the pending instruction into the re-order buffer, designating the entry as being written.

Reducing power consumption in a multi-slice computer processor

Methods and apparatus for preventing premature reads from a general purpose register (GPR) including receiving an instruction comprising a source operand identifying a source GPR entry; setting a read-enabled flag based on a value in a particular entry of a source ready vector; if the read-enabled flag indicates data in the source GPR entry is ready for reading, dispatching the received instruction, including performing a read operation of the data in the source GPR entry; and if the read-enabled flag indicates data in the source GPR entry is not ready for reading, dispatching the received instruction without performing a read operation of the data in the source GPR entry.

Preventing premature reads from a general purpose register

A multiplier engine that reduces the size of the circuitry used to provide the multiplier engine, as well as increases the speed at which the multiplication algorithm is performed, are provided. The illustrative embodiments may comprise a M*8 multiplication engine having one or more 4:2 compressors that comprise only two full adders, as opposed to the three full adders in the known 5:2 compressor based architecture. The 4:2 compressors are able to achieve the same operation as the known 5:2 compressor based architecture by virtue of using the unused bits in a least significant portion of the partial product inputs to store the negate bit values. Moreover, a negate bit value that is not fused with the partial product inputs may be input to the 4:2 compressors for a bitposition.

Multiplier engine

A Booth decoder may comprise three circuits that run in parallel. A first circuit is used to generate a shift control signal output. A second circuit is used to generate a zero control signal output. A third circuit is used to generate an invert control signal output. The first and second circuits receive the three-bit block as an input and generate their respective outputs based on the setting of each of the bits. The third circuit receives only the most significant bit of the three-bit block as its input and generates an invert signal output based on the setting of the most significant bit. In each of these circuits, the number of complex gates and transistors is minimized thereby reducing gate delay and power consumption in generating the control signals for performing a Booth multiplication operation.

Booth decoder apparatus and method

A design structure for a Booth decoder is provided. The Booth decoder may comprise three circuits that run in parallel. A first circuit is used to generate a shift control signal output. A second circuit is used to generate a zero control signal output. A third circuit is used to generate an invert control signal output. The first and second circuits receive the three-bit block as an input and generate their respective outputs based on the setting of each of the bits. The third circuit receives only the most significant bit of the three-bit block as its input and generates an invert signal output based on the setting of the most significant bit. In each of these circuits, the number of complex gates and transistors is minimized thereby reducing gate delay and power consumption in generating the control signals for performing a Booth multiplication operation.

Design structure for a booth decoder

A configurable, low power high fan-in multiplexer (MUX) and design structure thereof are disclosed. The MUX circuit includes multiple current control elements, which each include multiple inverters coupled to a transmission gate. Each current control element receives a data signal and a select signal that corresponds to the data signal. If a select signal exceeds a threshold value (e.g., a logical '1'), the select signal deactivates a pull-up transistor (e.g., a p-type field effect transistor), and the transmission gate enables the corresponding data signal to provide input to a logic gate (e.g., a NAND gate) coupled to the output of the MUX. If the select signal does not exceed the threshold value, the select signal activates the pull-up transistor, and the transmission gate prevents the corresponding data signal from providing input to the logic gate.

Structure for a configurable low power high fan-in multiplexer

A technique for operating a multiplexer includes selecting, from multiple transmission gate groups, a transmission gate group. A transmission gate is selected from the selected transmission gate group. Finally, a data signal associated with the selected transmission gate is provided at an output of the multiplexer.

Transmission gate multiplexer

A technique for clock gating a clock domain of an integrated circuit includes storing first, second, and third values in a control register. The first value corresponds to a first number of clock cycles to wait before initiating clock gating, the second value corresponds to a second number of clock cycles in which clock gating is performed, and the third value corresponds to a third number of clock cycles in which clock gating is not performed. One of the first, second, and third values is selectively loaded from the control register into a counting circuit. The counting circuit counts from the loaded one of the first, second, and third values to a transition value. A compare signal is received at the control state machine (from the counting circuit) that indicates the counting circuit has reached the transition value. Based on a current state of the control state machine, a load signal is provided to the counting circuit to cause the counting circuit to load an associated one of the first, second, and third values from the control register.

Techniques for reducing power requirements of an integrated circuit

A configurable, low power high fan-in multiplexer (MUX) is disclosed. The MUX circuit includes multiple current control elements, which each include multiple inverters coupled to a transmission gate. Each current control element receives a data signal and a select signal that corresponds to the data signal. If a select signal exceeds a threshold value (e.g., a logical '1'), the select signal deactivates a pull-up transistor (e.g., a p-type field effect transistor), and the transmission gate enables the corresponding data signal to provide input to a logic gate (e.g., a NAND gate) coupled to the output of the MUX. If the select signal does not exceed the threshold value, the select signal activates the pull-up transistor, and the transmission gate prevents the corresponding data signal from providing input to the logic gate.

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Austin, TX, United States of America

Owen Chiang