Cirrus Logic Inc.

Altia Systems Inc

Gn Audio A/s

Faust Communications, LLC

Linkup Systems Corporation

Otto Sponring

Kameswaran Sivamani

Narasimha R Nookala

Yashket Gupta

Edmund Cheung

Naveed Alam

Aurangzeb Khan

Ram Natarajan

Robert J Hankinson

Sunil Kumar Madaan

A system for generating real-time panoramic video is disclosed. The system comprises a plurality of micro panoramic cameras which are enabled on a processing unit and which are configured to simultaneously capture video frames from each of the plurality of micro panoramic cameras, wherein the video frames captured by two consecutive camera sensors from the plurality of camera sensors include an overlapping field of view, synchronize and feed the captured images to the processing unit with equal predefined delay, stitch the video frames captured by each of the plurality of micro panoramic cameras and output a real-time panoramic video on a display.

Panoramic camera device

Panoramic camera enclosure

Camera carrier

Camera mount

Printed circuit board

An application specific integrated circuit (ASIC) has a clock controller that dynamically selects an appropriate clock frequency for a resource. The ASIC includes a central processing unit (CPU), on-chip memory, a memory controller controlling external memory devices, a system bus, and various peripheral controllers. Devices that can be accessed by other devices, such as the on-chip memory, the memory controller, and the system bus are 'resources.' The devices that access the resources are 'controllers.' The ASIC generates a master clock and the clock controller derives clocks for driving the resources and controllers from the master clock. A multiplexer (MUX) in the clock controller selects the clock that is passed to a resource. Each controller has a request line to the clock controller for signaling when the controller is accessing a resource. The clock controller has a programmable register for each controller holding a value representing the bandwidth utilization of the controller and an adder and a frequency table. The adder sums the contents of the bandwidth registers of the controllers that are accessing a resource. The sum is an index to an entry in a frequency table. The value held in the frequency table is applied to the selection inputs of the MUX to select the clock for the resource. If no controllers are requesting access to the memory controller, the clock controller shuts down the memory clock. Accordingly, the clock frequency of the resource is determined by the bandwidth utilization of the controllers requesting access to the resource.

System and method for dynamic clock generation

An application specific integrated circuit (ASIC) has a clock controller that dynamically selects an appropriate clock frequency for a resource. The ASIC includes a central processing unit (CPU), on-chip memory, a memory controller controlling external memory devices, a system bus, and various peripheral controllers. Devices that can be accessed by other devices, such as the on-chip memory, the memory controller, and the system bus are &ldquo;resources.&rdquo; The devices that access the resources are &ldquo;controllers.&rdquo; The ASIC generates a master clock and the clock controller derives clocks for driving the resources and controllers from the master clock. A multiplexer (MUX) in the clock controller selects the clock that is passed to a resource. Each controller has a request line to the clock controller for signaling when the controller is accessing a resource. The clock controller has a programmable register for each controller holding a value representing the bandwidth utilization of the controller and an adder and a frequency table. The adder sums the contents of the bandwidth registers of the controllers that are accessing a resource. The sum is an index to an entry in a frequency table. The value held in the frequency table is applied to the selection inputs of the MUX to select the clock for the resource. If no controllers are requesting access to the memory controller, the clock controller shuts down the memory clock. Accordingly, the clock frequency of the resource is determined by the bandwidth utilization of the controllers requesting access to the resource.

A mechanism to effectively retrieve residual data received from a serial data source is provided. As the shift register receives serial data from the serial data source, the activities and content of the shift register is monitored. Status bits are set to reflect the activities and content. These status bits are used to determine whether the shift register contains residual data and whether such residual data should be ignored the serial data received from the serial data source is output to a destination.

Method and arrangement to effectively retrieve residual data from a

A mechanism to allow dynamic configurations and/or diagnostic of a computer system from a remote location is provided. The computer system receives instruction codes of a program from a data source. When executed by the CPU, the instruction codes performs the necessary erase and program operations to embed a firmware program onto to the flash memory. The firmware program can be used for configurations or diagnostic purpose.

Self-booting mechanism to allow dynamic system configuration and

An arrangement, system, and method to allow a computer system to have a normal operating mode with full display capability and a low-power operating mode with reduced display capability is provided. The computer system automatically switches to the low-power operating mode from the normal operating mode following a programmable period of inactivity. While display data is retrieved from an external DRAM in the normal operating mode, display data is retrieved from an internal SRAM in the low-power operating mode. The computer system switches back to the normal operating mode when one of the predetermined activities is detected.

Arrangement, system, and method for automatic remapping of frame buffers

A video signal decoder using a sample clock tied to a frequency that is an integer multiple of four times the color subcarrier (4*Fsc). By using a 4*Fsc rate on a given input wave, the decoder determines the phase shift between the sample clock and the original wave being sampled. Then, the decoder calculates the color based upon that shift. Circuitry for implementing the decoder contains two major circuit paths. The decoding process consists of two main phases and each path performs a different function during each phase. During the first phase, the first path calculates constants based upon a user's hue and saturation adjustments used for chroma demodulation. Also during the first phase, the second path examines the color burst signal and from that signal finds the black level of the incoming video signal. During the second phase, the first path decodes the color in the TV signal using the constants calculated during the first phase. Also during the second phase, the second path pulls the luma information out of the signal line.

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Los Altos, CA, United States of America

Otto Sponring