International Business Machines Corporation

Otto Koblinger

Hans-Joachim Trumpp

Reinhold Muhl

Klaus Meissner

Werner Zapka

Werner Stoffler

Method for providing a metallization layer on an insulating layer and

Disclosed is a method for manufacturing a high-denisty multilayer metallization pattern on an integrated circuit structure. Also disclosed are integrated circuit structures made with such method. The components of the integrated circuit may be formed on the substrate using conventional processes. A first metallization pattern is then formed on the semiconductor substrate having at least one integrated circuit. Next, the first layer of a double-layer insulation is applied over the first metallization pattern, and a photoresist layer is applied over the first layer for planarizing the topology of the metallization pattern and for defining a pad mask by a photoprocess over a conductive pad. For planarization of the topology, the photoresist layer and the first layer of the double-layer insulation are reactive ion etched at substantially the same rate to a desired depth. This reactive ion etching step also removes the first layer of the double-layer insulation from the pad mask area thereby exposing a metal pad. On top of the planarized topology, the second layer of the double-layer insulation is applied, and vias are opened in the layer by a plurality of dry-etching steps. The second metalliation pattern is formed on this second layer. Then, another double-layer insulation is applied on top of the second metallization pattern, the first layer being an inorganic and the second layer an organic layer. After opening vias in the layers of this double-layer insulation by contour-etching, a third metallization pattern is applied. Optionally, a fourth metallization pattern can be formed on the integrated circuit structure.

Method for producing an integrated circuit structure with a dense

In the course of the process for making masks with structures in the submicrometer range, initially structures of photoresist or polymer material with horizontal and substantially vertical sidewalls are produced on a silicon substrate covered with an oxide layer. This is followed by a layer of silicon nitride which is deposited by LPCVD. The resultant structure is planarized with a photoresist which is etched back until the start of the vertical edges of the sidewall coating formed by the nitride layer is bared on the photoresist structures. In a photolithographic step, a trimming mask is produced on the surface of the nitride layer and the planarizing resist. The bared regions of the nitride layer are then removed by isotropic etching. The dimensions A-B of the openings defined after removal of the nitride layer from the vertical surfaces of the photoresist structures are transferred to the oxide layer by anisotropic etching. Concurrently with these structures of minimum line width, registration marks are generated which allow the adjustment necessary for a further photolithographic step to be carried out with maximum accuracy. After removal of the trimming mask, the planarizing resist, the photoresist structures and the remainder of the nitride layer, structures with coarser line widths are defined in a further photolithographic step, which are also transferred to the oxide layer. Using the oxide layer as a mask, trenches of the desired depth are produced in the silicon substrate by anisotropic etching. The mask is thinned by anisotropic etching, and the oxide layers are removed from the front and the back side by wet etching.

Process for making masks with structures in the submicron range

Disclosed is a method of producing an integrated semiconductor structure, comprising components with dimensions in the submicron range, wherein a three-layer resist system is used to produce a polymer or resist mask. The polymer or resist mask thus produced is used to etch a layer of polysilicon on the semiconductor substrate. The method is characterized in that the pattern, produced conventionally in the top layer of the three-layer resist and including an angle &lt; about 90.degree., is transferred by RIE, using CF.sub.4, to the center layer of plasma nitride and by RIE, using oxygen, to the bottom resist or polymer layer. In a prior art method, this was followed by lateral etching in oxygen to reduce the dimensions of the mask by a desired amount. The improved method of the invention provides for the plasma nitride mask to be removed first, using, if necessary a facetting step in oxygen to increase the positive angle in the mask structure, and then for the latter structure to be laterally etched in oxygen to reduce its dimensions by the desired amount. As the angle in the mask is &lt; about 90.degree., the parameters for lateral etching may be chosen such that the etch process is largely anisotropic and, thus, accurately and readily determinable. As a result, the absolute amount of lateral etching may be accurately adjusted during the etch period. As shading plasma nitride is removed before lateral etching, the influence of neighboring structures on lateral etching is largely reduced. The mask thus produced is used to etch in the polysilicon layer structures whose angles ensure a good definition of the spacers to be produced in the subsequent process steps and of ion implantation, which both determine the effective channel length of field-effect transistors.

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Korntal-Munchingen, Germany

Otto Koblinger