Rca Inc.

Harris Corporation

General Electric Company

Harris Semiconductor Patents Inc.

Otto H Schade, Jr

An integrated circuit for providing a current proportional to absolute temperature comprises circuitry for providing a first current exhibiting substantially zero temperature coefficient; circuitry for providing a second current exhibiting a negative temperature coefficient; and circuitry for summing the first and second currents for providing a third current proportional to absolute temperature.

Circuit for providing a current proportional to absolute temperature

A non-linear current mirror amplifier includes a master diode-connected transistor in series with a resistor to provide a forward diode bias and a resistive drop. A slave transistor is forward biased by the forward diode bias and the resistive drop. A current splitter applies a fraction of an input current to the master diode-connected transistor.

Non-linear operational transconductance amplifier

The accuracy of a bandgap type reference voltage generator which contains bipolar load elements is increased by the use of current compensation circuitry which includes a dummy load element which is the electrical equivalent of the load elements of the generator, an operational amplifier and a current mirror. The operational amplifier and the current mirror act to cause the same potential level (voltage) to be applied to the dummy load element as is applied to the load elements of the generator. A master leg of the current mirror generates a first output current which is identical to the current drawn by the load elements of the generator and provides the current to the dummy load element. A slave leg of the current mirror generates a second output current which is identical to the first output current and which is coupled to the load elements of the generator. Thus current used to drive the load elements of the generator is supplied by the compensation circuitry. This improves the accuracy of the output voltage generated by the reference voltage generator.

Transistor base current compensation circuitry

A bipolar transistor includes a substrate of semiconductor material having an expitaxial body of the semiconductor material on a surface thereof. The semiconductor body has a major surface. A collector region of one conductivity type is in the body at the major surface and a base region of the opposite conductivity type is in the collector region at the major surface and forms with the collector region a collector/base junction which extends to the surface. A plurality of emitter regions of the one conductivity type are in the base region and form with the base region emitter/base junctions which extend to the surface. At least some of the emitter/base junctions are adjacent to but spaced from the collector/base junction at the major surface. A layer of insulating silicon oxide is on the major surface and a layer of conductive polysilicon is on the insulating layer. The polysilicon layer includes strips which extend only over the area of the surface between the collector/base junction and the adjacent emitter/base junctions and resistor areas to which the strips are connected. The emitter regions are connected to the polysilicon layer. The bipolar transistor may be part of an integrated circuit which includes MOS transistors and the polysilicon layer also forms the gates of the MOS transistors.

Bipolar transistor with field shields

Imbalances in the potential appearing across the drain electrodes of source coupled FET transistors arranged in a differential amplifier configuration tends to produce input offset voltages. Where the drain electrodes of the transistors are coupled to a current mirror load for converting balanced signals to a single ended output which in turn is applied to a common source amplifier, the input offset may be nulled by differentially adjusting the drain current of the common source amplifier against the source current of the differential stage.

Trimming circuits for precision amplifier

A two phase waveform generator for producing nonoverlapping pulses is designed with a CMOS inverter modified to include a resistor between the drain electrodes of the complementary inverter transistors and three conventional CMOS inverter circuits. The resistor n-type transistor interconnection exhibits a fast negative signal transition but a slower positive transition due to the resistor. This effect tends to shorten the duration of pulses applied to the inverter input. The shortened pulses are applied to a cascade connected pair of inverters to sharpen the waveform and produce a first phase output signal. The resistor-p-type transistor interconnection of the modified inverter exhibits a fast positive signal transition but a slower negative transition. This effect tends to widen pulses applied to the input. The widened pulses are applied to another inverter which complements the widened pulses ultimately generating narrower pulses which comprise a second phase signal. The first and second phase signals are antiphase with no pulse overlap.

Circuitry for generating non-overlapping pulse trains

A threshold comparator for use with a dual slope A/D converter has its input potential established at its threshold potential during auto-zeroing. Potential offset means is included in the auto-zero feedback loop around the integrating and output amplifiers of the A/D circuit. Bias current applied to the potential offset means substantially tracks current passed in the comparator so that the potential developed by the potential offset means substantially tracks the threshold potential of the comparator.

Offset compensation apparatus for biasing an analog comparator

A differential amplifier is arranged to exhibit substantially no D.C. offset or drift. Input signal is alternately connected to the non-inverting and inverting input terminals of an input differential stage. Synchronously therewith the differential output signals of the differential stage are interchanged to maintain the sense of the output signal constant. The synchronous interchanging of differential input and differential output signals tends to average out parameter offset in the input circuit elements. The differential input stage is provided with a substantially balanced active current mirror load. The current mirror load devices are commutated with respect to the input devices to further reduce amplifier offset arising inherently in the differential stage load elements. The commutation of the current mirror load elements is performed at a rate which is a multiple of the rate at which the input and output signals are interchanged.

Low drift amplifier

A current amplifier includes six transistors of like conductivity on a substrate, the first and second transistors being diode-connected to receive input current, and the third and fourth having their main conduction paths serially connected with those of the first and second transistors, respectively. The gates of the third and fourth transistors are cross coupled with their drains. The gate-source connections of the fifth and sixth transistors are respectively connected in parallel with the gate-source connections of the third and fourth transistors. A potentiometer connects the respective sources of the third and fourth transistors to a common terminal for adjusting the relative portion of the input current in the aforementioned main conduction paths, thereby to proportionally adjust the drain currents of the fifth and sixth transistors.

Temperature-independent current trimming arrangement

A current mirror amplifier includes first and second transistors connected together at their common electrodes, the first transistor being connected for receiving input signal current at its output electrode, and the control electrodes of the transistors being connected for conditioning the second transistor for conducting a current responsive to the input signal current. Switch means, responsive to a control signal, selectively connects the output electrode of the second transistor to a supply terminal so the current gain between the input signal current and the current in the connection of their common electrodes switches responsive to the control signal.

Current mirror amplifiers with programmable gain

An operational amplifier includes a differential-input amplifier stage supplying first and second drive currents responsive to input signals applied to its input connections. A first current amplifier exhibiting gain factor G supplies currents to an output terminal responsive to the first drive current, and a second current amplifier exhibiting gain factor H supplies currents to that output terminal responsive to the second drive current. Each of the first and second current amplifiers includes means for switching the value of its respective gain factor G or H between a plurality of values responsive to a control signal, so the gain of the operational amplifier is programmable responsive to the control signal.

Operational amplifier with programmable gain

The input offset potential of a transistor amplifier exhibited by a grounded-emitter bipolar transistor or a grounded source enhancement-mode field effect transistor can be too large for certain applications. A preceding differential-input amplifier overcomes this problem.

Transistor amplifiers exhibiting low input offset potentials

A current mirror amplifier comprising a master mirroring transistor with collector-to-base connection for adjusting its emitter-to-base potential to condition it to conduct input current applied to its collector-emitter path, a plurality of slave mirroring transistors arranged to respond to an emitter-to-base potential equal to that of the master mirroring transistor for conducting an output current through its emitter-collector path proportional to the input current, a further transistor with its collector-emitter path arranged to sense the collector current of one of the slave mirroring transistors, and a component current mirror amplifier responding to the base current of the further transistor flowing through its input connection to supply a substantial share of the base current needs of said mirroring transistors at its output connection.

Compensation of base-current-related error in current mirror amplifier

A differential-input amplifier suitable for the input stage of a CMOS operational amplifier has the capability of amplifying input signals with common-mode voltage components in a range including the entirety of its operating voltage. To provide this capability for one end of the common-mode range a long-tailed pair connection of depletion-mode field effect transistors with gates at the inverting and non-inverting input terminals of the amplifier is used; and to provide this capability for the other end of the common-mode range the substrates of the transistors are biased to operate them in effect as enhancement-mode transistors allowing their drains to work into a current mirror amplifier used for converting their balanced drain variations to single-ended form. Current mirror amplifier configurations are disclosed which are preferable for such conversion since they operate with reduced potential requirements, but are integrable in CMOS.

Differential-input amplifier circuitry with increased common-mode

In addition to the usual field-effect transistor structures available in CMOS-type integrated circuitry, certain bipolar transistor structures are also available for use in linear amplifier circuits combining both bipolar and FET devices. One of the transistor structures available, i.e., a vertical transistor, has high current gain but its collector region, integral to the substrate, is committed to substrate potential. The other of the bipolar transistor structures available, i.e., a lateral transistor, has an uncommitted collector, but has low current gain. A cascade connection of both bipolar transistor types provides a composite transistor with high current gain and uncommitted collector useful in combination with field-effect transistor structures to form novel amplifier arrangements.

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North Caldwell, NJ, United States of America

Otto H Schade, Jr