International Business Machines Corporation

Globalfoundries Inc.

Other

Otto Andreas Torreiter

Martin Eckert

Thomas Gentner

Quintino Lorenzo Trianni

Dieter F Wendel

Roland Frech

Juergen Pille

Michael B Kugel

Thomas Strach

Jochen Supper

Jens Kuenzer

Eckhard Kunigkeit

Antje Mueller

Alejandro Alberto Cook Lobo

Manfred Schmidt

Tobias Werner

David T Hui

Thomas-Michael Winkel

Daniel Rodko

Sebastian Ehrenreich

Roland Dieterle

Siegfried Tomaschko

Hagen Schmidt

Joseph E Eckelman

Ulrich Baur

Gabriele Kuczera

Joerg Georg Appinger

Eberhard Dengler

Roland Metzger

Claudio Siviero

Nils Schlemminger

Christian Zoellin

Gottfried Andreas Goldrian

Matthias Pflanz

Joachim Kneisel

Ulrich Diebold

Hans Wiedemann

Ulich Diebold

Rolf Vogt

Jörg Georg Appinger

Klaus Wagner-Drebenstedt

Peter Rost

A method for testing at least one single chip in a wafer probing system, at least comprising: providing an adapter plate having an interface surface for contacting a vacuum chuck of the wafer probing system, the adapter plate being configured to accommodate the at least one single chip in a cutout with a chip rear surface being flush with the interface surface; loading the adapter plate with the at least one single chip into the wafer probing system; determining an exact position of the at least one single chip in the adapter plate in the search area; and testing the at least one single chip with test routines stored in a controller of the wafer probing system. A device and an adapter plate for testing at least one single chip in a wafer probing system.

Testing a single chip in a wafer probing system

A tool for performing a logic built-in self-test of an electronic circuit operating on a clock cycle basis. The tool stores a configurable test signature in a random-access memory together with a pattern counter for a test pattern, wherein a number of the at least one additional signature register corresponds to a number of entries in the random access memory. The tool determines an error based, at least in part, on a compare operation for a given test pattern, wherein the compare operation determines whether the test signature in the first signature register before a capture cycle of a next test pattern differs from the corresponding configurable test signature. The tool stores the error in a corresponding additional signature register.

Logic built-in self-test of an electronic circuit

The invention relates to a device for positioning a semiconductor die in a wafer prober, the device comprising a carrier plate and a clamp on a front surface of the carrier plate, the dimensions of the carrier plate matching a standard geometry required by the wafer prober for receiving a semiconductor wafer to be probed by the wafer prober, the clamp being reversibly movable against a force of an elastic element between an open position and a closed position, the clamp being adapted for fixing the die on the carrier plate in the closed position and for releasing the die in the open position.

Device for positioning a semiconductor die in a wafer prober

The invention relates to an integrated circuit with an active transistor area and a plurality of wiring layers arranged above the active transistor area. At least one optical device is integrated in the active transistor area. The optical device is electrically connected with at least one of the wiring layers. At least one optical tunnel extends from the at least one optical device through the plurality of wiring layers to a surface of an uppermost wiring layer of the plurality of wiring layers facing away from the active transistor area.

Integrated circuit with optical tunnel

Various aspects of the present invention disclose a test device that includes a retaining element retaining one or more nuclear radiation sources for performing a nuclear radiation stress test of data storage structures of integrated circuits on a wafer in a wafer prober. The retaining element includes one or more apertures for applying nuclear radiation from the one or more nuclear radiation sources to the data storage structures. The retaining element is configured for controlling the nuclear radiation applied via the one or more apertures. The controlling includes a varying of relative positions of the one or more nuclear radiation sources and the one or more apertures. Additional aspects of the present invention disclose a testing method, computer program product, and computer system for performing the nuclear radiation stress test. In an example aspect, embodiments of the present invention disclose a test device for a wafer prober.

Stressing integrated circuits using a radiation source

An integrated circuit with a hardware-based controller enables a system for a set of clock cycles and selectively enables an aspect of the system for a subset of the set of clock cycles. The controller includes a clock cycle select circuit to output a test select signal that indicates the subset of the set of clock cycles during which to enable the aspect of the system, and a test start circuit to receive the test select signal and output a test signal to the system to enable the system for the set of clock cycles. The controller also includes an AND gate to output a gated signal to enable the aspect of the system for the subset of the set of clock cycles based on the test select signal.

On-chip hardware-controlled window strobing

A system for layout effect characterization of an integrated circuit includes a memory having computer readable instructions and a processor for executing the computer readable instructions. The computer readable instructions include selecting an adjustable clock setting of an input clock for a layout effect characterization circuit of the integrated circuit and enabling a predetermined duty cycle of the input clock to pass through a plurality of inverting device chains including a reference chain and one or more chains having a different inverting device arrangement and a same number of inverting devices per chain. The computer readable instructions also include measuring a captured output of the one or more chains having the different inverting device arrangement and a captured output of the reference chain.

Layout effect characterization for integrated circuits

A method for electrical testing of a 3-D integrated circuit chip stack is described. The 3-D integrated circuit chip stack comprises at least a first integrated circuit chip and a second integrated circuit chip. The first integrated circuit chip and the second integrated circuit chip are not soldered together for performing electrical testing.

Method for electrical testing of a 3-D chip stack

A chip attach frame is used to align pins of an integrated circuit chip with pads on a chip carrier. A frame block has a socket defining two alignment edges that form a reference corner. The chip is lowered into the socket, and the chip carrier is inclined while it supports the frame block and chip until the chip moves under force of gravity to the reference corner. Once located at the reference corner, the chip position is carefully adjusted by moving the frame block in the x- and y-directions until the pins are aligned with the pads. The frame block is spring biased against movement in the x- and y-directions, and the position of the frame block is adjusted using thumbscrews. A plunger mechanism can be used to secure the integrated circuit chip in forcible engagement with the chip carrier once the pins are aligned with the pads.

Chip attach frame

A wafer probe alignment system and method for aligning a probe to a chip wafer for testing a chip on the wafer are provided. At least two corners of the probe are adjustable in a same direction in relation to a primary corner of the probe. The alignment approach includes providing a grid of signal pins for corresponding contact pads of the chip under test, determining for each signal pin whether an electrical contact is established to a corresponding contact pad of the chip under contact force, and adjusting a position of each of the at least two corners by a corner individual delta position value with respect to the direction depending on a result of the determining in order to establish an electrical contact between each of the pins and the corresponding contact pads of the chip under test.

Wafer probe alignment

A water probe alignment system and method for aligning a probe to a chip wafer for testing a chip on the wafer are provided. At least two corners of the probe are adjustable in a same direction in relation to a primary corner of the probe. The alignment approach includes providing a grid of signal pins for corresponding contact pads of the chip under test, determining for each signal pin whether an electrical contact is established to a corresponding contact pad of the chip under contact force, and adjusting a position of each of the at least two corners by a corner individual delta position value with respect to the direction depending on a result of the determining in order to establish an electrical contact between each of the pins and the corresponding contact pads of the chip under test.

A layout effect characterization circuit includes a plurality of inverting device chains including a reference chain and one or more chains having a different inverting device arrangement and a same number of inverting devices per chain. A low pass filter is coupled to an output of the inverting device chains to produce a filtered output. An output capture circuit is coupled to the filtered output to enable a comparison of a captured filtered output of the one or more chains having the different inverting device arrangement to a captured filtered output of the reference chain.

An aspect includes forming a layout effect characterization circuit by incorporating a plurality of inverting device chains including a reference chain and one or more chains having a different inverting device arrangement and a same number of inverting devices per chain in an integrated circuit layout. A low pass filter is coupled to an output of the inverting device chains to produce a filtered output. An output capture circuit is coupled to the filtered output to enable a comparison of a captured filtered output of the one or more chains having the different inverting device arrangement to a captured filtered output of the reference chain.

Growing community of inventors

Leinfelden-Echterdingen, Germany

Otto Andreas Torreiter